QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 851
10/12/14 BIT 10 TO 105 MSPS ADC
5
APPLYING POWER AND SIGNALS TO THE DC851
DEMONSTRATION CIRCUIT BOARD:
If a DC890 is used to acquire data from the DC851,
the DC890 should be powered up FIRST, before ap-
plying +3V across the pins marked “+3.0V” and
“PWR GND” on the DC851. However, the output
buffers on DC851 will not be enabled until power is
applied to DC890. The DC851 demonstration circuit
requires up to 200 mA depending on the sampling
rate and the A/D converter supplied.
ENCODE CLOCK
NOTE: This is not a logic compatible input. It is
terminated with 50 Ohms. Apply an encode clock
to the SMA connector on the DC851 demonstration
circuit board marked “J3 CLOCK INPUT”. This input
is connected to ground through a 50Ω resistor, and
followed by a blocking capacitor. For the best noise
performance, the CLOCK INPUT must be driven
with a very low jitter source. When using a sinusoi-
dal generator, the amplitude should be as large as
possible, up to 3V
P-P
or 13 dBm. Using band pass
filters on the clock and the analog input will im-
prove the noise performance by reducing the wide-
band noise power of the signals. Data sheet FFT
plots are taken with 10 pole LC filters made by TTE
(Los Angeles, CA) to suppress signal generator
harmonics, non-harmonically related spurs and
broad band noise. Low phase noise Agilent 8644B
generators are used with TTE band pass filters for
both the Clock input and the Analog input.
A square wave encode clock is recommended for
sample rates lower than 20MSPS. This is because
the lower slew rate of a sinusoidal encode clock
translates to increased clock jitter and hence lower
SNR.
The Encode Clock can be driven with a 2.5V CMOS
Logic Level square wave if R14 is replaced with an
acceptable load for the drive capability of the logic.
Note that logic devices are generally not able to
drive cable. A barrel is recommended for logic
drive. If a cable is used, the cable carrying the clock
signal must be terminated to maintain the signal
integrity of the Encode Clock Source and the signal
source must be able to drive the 0 to 2.5V square
wave signal into 50Ω load.
ANALOG INPUT NETWORK
Apply the analog input signals of interest to the
SMA connectors on the DC851 demonstration cir-
cuit board marked “ANALOG INPUT (A and B)”.
These inputs are capacitively coupled to ETC1-1-13
Balun transformers on high input frequency ver-
sions, or directly coupled through ETC1-1T Flux
coupled transformers on low input frequency ver-
sions.
For optimal distortion and noise performance the
RC network on the analog inputs are optimized for
different analog input frequencies on the different
versions of the DC851. For input frequencies below
about 100 MHz, the circuit in Fig. 2 is recom-
mended (this is installed on DC851 versions A, B,
C, D, E, H, I, J, K, L, O, P, Q, R, S, U, W). For input
frequencies above 100 MHz and below 250 MHz,
the circuit in Fig. 3 is recommended (this is in-
stalled on versions F, G, M, N, T, V, X).
For input frequencies greater than 300 MHz, the
circuit in Fig. 4 is recommended. For input fre-
quencies greater than 250 MHz contact the factory
for support.
