NCP1579
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7
UVLO
Undervoltage Lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when V
CC
is too low to
support the internal rails and power the converter. For the
NCP1579, the UVLO is set to permit operation when
converting from a 5.0 input voltage.
Overcurrent Threshold Setting
NCP1579 can easily program an Overcurrent Threshold
ranging from 50 mV to 550 mV, simply by adding a resistor
(RSET) between BG and GND. During a short period of
time following V
CC
rising over UVLO threshold, an internal
10 mA current (I
OCSET
) is sourced from BG pin,
determining a voltage drop across R
OCSET
. This voltage
drop will be sampled and internally held by the device as
Overcurrent Threshold. The OC setting procedure overall
time length is about 6 ms. Connecting a R
OCSET
resistor
between BG and GND, the programmed threshold will be:
I
OCth
+
I
OCSET
@ R
OCSET
R
DS(on)
(eq. 1)
RSET values range from 5 kW to 55 kW. In case R
OCSET
is not connected, the device switches the OCP threshold to
a fixed 375 mV value: an internal safety clamp on BG is
triggered as soon as BG voltage reaches 700 mV, enabling
the 375 mV fixed threshold and ending OC setting phase.
The current trip threshold tolerance is ±25 mV. The accuracy
of the set point is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases.
Current Limit Protection
In case of a short circuit or overload, the lowside (LS)
FET will conduct large currents. The controller will shut
down the regulator in this situation for protection against
overcurrent. The lowside R
DS(on)
sense is implemented at
the end of each of the LSFET turnon duration to sense the
over current trip point. While the LS driver is on, the Phase
voltage is compared to the internally generated OCP trip
voltage. If the phase voltage is lower than OCP trip voltage,
an overcurrent condition occurs and a counter is initiated.
When the counter completes, the PWM logic and both
HSFET and LSFET are turned off. The controller has to
go through a Power On Reset (POR) cycle to reset the OCP
fault.
Drivers
The NCP1579 includes gate drivers to switch external
Nchannel MOSFETs. This allows the devices to address
highpower as well as lowpower conversion requirements.
The gate drivers also include adaptive nonoverlap
circuitry. The nonoverlap circuitry increase efficiency,
which minimizes power dissipation, by minimizing the
body diode conduction time.
A detailed block diagram of the nonoverlap and gate
drive circuitry used in the chip is shown in Figure 9.
Figure 9. Block Diagram
BST
TG
PHASE
BG
GND
R
set
FAULT
FAULT
8
2
1
4
3
V
CC
2 V
-
+
-
+
Careful selection and layout of external components is
required, to realize the full benefit of the onboard drivers.
The capacitors between V
CC
and GND and between BST
and SWN must be placed as close as possible to the IC. The
current paths for the TG and BG connections must be
optimized. A ground plane should be placed on the closest
layer for return currents to GND in order to reduce loop area
and inductance in the gate drive circuit.
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8
APPLICATION SECTION
Input Capacitor Selection
The input capacitor has to sustain the ripple current
produced during the on time of the upper MOSFET, so it
must have a low ESR to minimize the losses. The RMS value
of this ripple is:
Iin
RMS
+ I
OUT
D (1 * D)
Ǹ
,
where D is the duty cycle, Iin
RMS
is the input RMS current,
& I
OUT
is the load current. The equation reaches its
maximum value with D = 0.5. Loss in the input capacitors
can be calculated with the following equation:
P
CIN
+ ESR
CIN
Iin
RMS
2
,
where P
CIN
is the power loss in the input capacitors &
ESR
CIN
is the effective series resistance of the input
capacitance. Due to large dI/dt through the input capacitors,
electrolytic or ceramics should be used. If a tantalum must
be used, it must by surge protected. Otherwise, capacitor
failure could occur.
Calculating Input Start-up Current
To calculate the input start up current, the following
equation can be used.
I
inrush
+
C
OUT
V
OUT
t
SS
,
where I
inrush
is the input current during start-up, C
OUT
is the
total output capacitance, V
OUT
is the desired output voltage,
and t
SS
is the soft start interval.
If the inrush current is higher than the steady state input
current during max load, then the input fuse should be rated
accordingly, if one is used.
Calculating Soft Start Time
To calculate the soft start time, the following equation can
be used.
t
ss
+
(C
p
) C
c
)*DV
I
ss
Where C
c
is the compensation as well as the soft start
capacitor,
C
p
is the additional capacitor that forms the second pole.
I
ss
is the soft start current
DV is the comp voltage from zero to until it reaches
regulation
Vcomp
880 mV
Vout
DV
The above calculation includes the delay from comp
rising to when output voltage starts becomes valid.
To calculate the time of output voltage rising to when it
reaches regulation; DV is the difference between the comp
voltage reaching regulation and 0.88 V.
Output Capacitor Selection
The output capacitor is a basic component for the fast
response of the power supply. In fact, during load transient,
for the first few microseconds it supplies the current to the
load. The controller immediately recognizes the load
transient and sets the duty cycle to maximum, but the current
slope is limited by the inductor value.
During a load step transient the output voltage initial
drops due to the current variation inside the capacitor and the
ESR. ((neglecting the effect of the effective series
inductance (ESL)):
DV
OUTESR
+ DI
OUT
ESR
COUT
where V
OUT- ESR
is the voltage deviation of V
OUT
due to the
effects of ESR and the ESR
COUT
is the total effective series
resistance of the output capacitors.
A minimum capacitor value is required to sustain the
current during the load transient without discharging it. The
voltage drop due to output capacitor discharge is given by
the following equation:
DV
OUTDISCHARGE
+
DI
OUT
2
L
OUT
2 C
OUT
(V
IN
D * V
OUT
)
,
where V
OUT- DISCHARGE
is the voltage deviation of V
OUT
due to the effects of discharge, L
OUT
is the output inductor
value & V
IN
is the input voltage.
It should be noted that ΔV
OUT- DISCHARGE
and
ΔV
OUT- ESR
are out of phase with each other, and the larger
of these two voltages will determine the maximum deviation
of the output voltage (neglecting the effect of the ESL).
Inductor Selection
Both mechanical and electrical considerations influence
the selection of an output inductor. From a mechanical
perspective, smaller inductor values generally correspond to
smaller physical size. Since the inductor is often one of the
largest components in the regulation system, a minimum
inductor value is particularly important in
space-constrained applications. From an electrical
perspective, the maximum current slew rate through the
output inductor for a buck regulator is given by:
SlewRate
LOUT
+
V
IN
* V
OUT
L
OUT
This equation implies that larger inductor values limit the
regulators ability to slew current through the output
inductor in response to output load transients. Consequently,
output capacitors must supply the load current until the
inductor current reaches the output load current level. This
results in larger values of output capacitance to maintain
NCP1579
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9
tight output voltage regulation. In contrast, smaller values of
inductance increase the regulators maximum achievable
slew rate and decrease the necessary capacitance, at the
expense of higher ripple current. The peak-to-peak ripple
current for NCP1579 is given by the following equation:
Ipk * pk
LOUT
+
V
OUT
(1 * D)
L
OUT
275 kHz
,
where Ipk-pk
LOUT
is the peak to peak current of the output.
From this equation it is clear that the ripple current increases
as L
OUT
decreases, emphasizing the trade-off between
dynamic response and ripple current.
Feedback and Compensation
The NCP1579 allows the output of the DC-DC converter
to be adjusted from 0.8 V to 5.0 V via an external resistor
divider network. The controller will try to maintain 0.8 V at
the feedback pin. Thus, if a resistor divider circuit was
placed across the feedback pin to V
OUT
, the controller will
regulate the output voltage proportional to the resistor
divider network in order to maintain 0.8 V at the FB pin.
FB
R1
R2
V
OUT
The relationship between the resistor divider network above
and the output voltage is shown in the following equation:
R
2
+ R
1
ǒ
V
REF
V
OUT
* V
REF
Ǔ
Resistor R1 is selected based on a design tradeoff between
efficiency and output voltage accuracy. For high values of
R1 there is less current consumption in the feedback
network, However the trade off is output voltage accuracy
due to the bias current in the error amplifier. The output
voltage error of this bias current can be estimated using the
following equation (neglecting resistor tolerance):
Error% +
0.1 mA R
1
V
REF
100%
Once R1 has been determined, R2 can be calculated.
Gm
EA
Figure 10. Type II Transconductance Error
Amplifier
R
1
R
2
V
ref
+
C
p
C
c
R
c
Figure 10 shows a typical Type II transconductance error
amplifier (EOTA). The compensation network consists of
the internal error amplifier and the impedance networks ZIN
(R
1
, R
2
) and external Z
FB
(R
c
, C
c
and C
p
). The
compensation network has to provide a closed loop transfer
function with the highest 0 dB crossing frequency to have
fast response (but always lower than F
SW
/8) and the highest
gain in DC conditions to minimize the load regulation. A
stable control loop has a gain crossing with -20 dB/decade
slope and a phase margin greater than 45°. Include
worst-case component variations when determining phase
margin. Loop stability is defined by the compensation
network around the EOTA, the output capacitor, output
inductor and the output divider. Figure 11 shows the open
loop and closed loop gain plots.
Compensation Network Frequency:
The inductor and capacitor form a double pole at the
frequency
F
LC
+
1
2p L
o
C
o
Ǹ
The ESR of the output capacitor creates a “zero” at the
frequency,
F
ESR
+
1
2p ESR C
o
The zero of the compensation network is formed as,
F
Z
+
1
2p R
c
C
c
The pole of the compensation network is calculated as,
F
p
+
1
2p R
c
C
p
Figure 11. Gain Plot of the Error Amplifier
Thermal Considerations
The power dissipation of the NCP1579 varies with the
MOSFETs used, V
CC
, and the boost voltage (V
BST
). The
average MOSFET gate current typically dominates the
control IC power dissipation. The IC power dissipation is
determined by the formula:
P
IC
+ (I
CC
V
CC
) ) P
TG
) P
BG
Where:

NCP1579DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers BUCK CONTROLLER
Lifecycle:
New from this manufacturer.
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