www.austriamicrosystems.com/LCD-Driver-ICs/AS1120 Revision 1.06 8 - 13
AS1120
Datasheet - Detailed Description
The selection of internal or external backplane signal (see Table 5) is initiated after RESETN is disabled – the first ris-
ing edge at pin OSC after RESETN is disabled will force pin BPLOUT to deliver the internally generated backplane sig-
nal. If there is no rising edge at pin OSC, BPLOUT will simply buffer the signal at pin BPLIN.
Note: The LCD should never be supplied with static signals. Verify that signals at pins BPLIN and BPLOUT are
always running while V
DD is supplied; note that pin BPLOUT is stopped during a reset.
Internal Mode – R/C Oscillator Running (Generating the Backplane)
Connect external R/C components to pin OSC as shown in Figure 1 on page 1. When an external REXT and CEXT are
connected to pin OSC, a clock signal whose frequency is equal to fOSC divided by 16 will be present at pin BPLOUT.
Note: Internal mode requires that pin BPLIN be connected to pin BPLOUT.
The oscillation period is approximately t
OSC = 1/fOSC = 0.69 x REXT x CEXT, and the error between the expected fre-
quency and the generated frequency increases as indicated in Table 6.
Figure 7. AS1120 Clock Circuit
External Mode: R/C Oscillator Stopped (External Backplane)
Connect pin OSC to VSS in order to block the internal oscillator. In this external mode, an external backplane signal
should be presented at pin BPLIN, which will be regenerated and presented at pin BPLOUT.
Table 5. Backplane Source Generation Selection
Mode OSC Pin BPLOUT
Internal Running f
OSC/16
External Tied Low BPLIN
Table 6. Oscillator Error Rate
Expected Oscillator Frequency Error
1 kHz 1%
10 kHz 5%
50 kHz 20%
100 kHz 40%
Oscillator
CLRN
fOSC/16
CLRN
SEL
D
Q
AS1120
15
OSC
43
VDD
11
BPLIN
13
RESETN
12
BPLOUT
A
B
