ADRF5025 Data Sheet
Rev. A | Page 4 of 13
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT LINEARITY
1
5 MHz to 40 GHz
1 dB Power Compression P1dB 27.5 dBm
Third-Order Intercept IP3 Two tone input power = 12 dBm each tone,
Δf = 1 MHz
50 dBm
SUPPLY CURRENT VDD and VSS pins
Positive Supply Current I
DD
14 µA
Negative Supply Current I
SS
120 µA
DIGITAL CONTROL INPUTS CTRL pin
Voltage
Low V
INL
0 0.8 V
High V
INH
1.2 3.3 V
Current
Low and High I
INL
, I
INH
<1 µA
RECOMMENDED OPERATING CONDITONS
Supply Voltage
Positive V
DD
3.15 3.45 V
Negative V
SS
−3.45 −3.15 V
Digital Control Voltage V
CTL
0 V
DD
V
RF Input Power
2
P
IN
f = 5 MHz to 40 GHz, T
CASE
= 85°C
3
Through Path RF signal is applied to RFC or through
connected RF1/RF2
27 dBm
Hot Switching RF signal is present at RFC while switching
between RF1 and RF2
27 dBm
Case Temperature T
CASE
−40 +105 °C
1
For input linearity performance over frequency, see Figure 13 to Figure 16.
2
For power derating over frequency, see Figure 2 and Figure 3.
3
For 105°C operation, the power handling degrades from the T
CASE
= 85°C specification by 3 dB.
Data Sheet ADRF5025
Rev. A | Page 5 of 13
ABSOLUTE MAXIMUM RATINGS
For the recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Positive Supply Voltage −0.3 V to +3.6 V
Negative Supply Voltage 3.6 V to +0.3 V
Digital Control Input Voltage 0.3 V to VDD + 0.3 V
RF Input Power (f = 5 MHz to 40 GHz,
T
CASE
= 85°C
1
)
27.5 dBm
27.5 dBm
Temperature
Junction, T
J
135°C
Storage Range 65°C to +150°C
Reflow 260°C
ESD Sensitivity
Human Body Model (HBM)
RFC, RF1, and RF2 Pins 1000 V
Digital Pins 2000 V
Charged Device Model (CDM) 1250 V
1
For 105°C operation, the power handling degrades from the T
CASE
= 85°C
specification by 3 dB.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one
time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θ
JC
is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type θ
JC
Unit
CC-12-3, Through Path 352 °C/W
POWER DERATING CURVES
16011-002
–14
–12
–10
–6
–4
–2
–8
0
2
10k 100k 1M 10M 100M 1G 10G 100G
POWER DERATING (dB)
FREQUENCY (Hz)
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, T
CASE
= 85°C
–14
–12
–6
–8
–10
–4
–2
0
2
35 38 44 5041 47
POWER DERATING (dB)
FREQUENCY (GHz)
1601
1-003
Figure 3. Power Derating vs. Frequency, High Frequency Detail, T
CASE
= 85°C
ESD CAUTION
ADRF5025 Data Sheet
Rev. A | Page 6 of 13
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RF2
VSS
CTRL
VDD
RF1
GND
GND
GND
GND
GND
GND
RFC
NOTES
1. EXPOSED PAD MUST BE CONNECTED
TO THE RF/DC GROUND OF THE PCB.
1
2
3
4 5 6
7
8
9
101112
16533-004
ADRF5025
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 3, 4, 6, 10, 12 GND Ground. These pins must be connected to the RF/dc ground of the PCB.
2 RFC RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
5 RF1 RF Port 1. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary when
the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
7 VDD Positive Supply Voltage.
8 CTRL Control Input Voltage. See Figure 6 for the interface schematic.
9 VSS Negative Supply Voltage.
11 RF2 RF Port 2. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary when
the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
INTERFACE SCHEMATICS
16533-005
RFC,
RF1,
RF2
Figure 5. RFx Pins Interface Schematic
VDD
VDD
CTRL
16533-006
Figure 6. CTRL Interface Schematic

ADRF5025BCCZN

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Switch ICs 40 GHz, Low Loss, Reflective, low cut oh
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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