AMIS−30663
http://onsemi.com
7
Table 7. DC Characteristics
(V
CC
= 4.75 to 5.25 V; V
33
= 2.9 V to 3.6 V; T
junc
= −40 to +150°C; R
LT
= 60 W unless specified otherwise.)
Symbol UnitMax.Typ.Min.ConditionsParameter
Bus Lines (pins CANH and CANL)
R
i(dif)
Differential input resistance 25 50 75
KW
C
i(CANH)
Input capacitance at pin CANH V
TxD
= V
CC
; not tested 7.5 20 pF
C
i(CANL)
Input capacitance at pin CANL V
TxD
= V
CC
; not tested 7.5 20 pF
C
i(dif)
Differential input capacitance V
TxD
= V
CC
; not tested 3.75 10 pF
I
LI(CANH)
Input leakage current at pin CANH V
CC
= 0 V; V
CANH
= 5 V 10 170 250
mA
I
LI(CANL)
Input leakage current at pin CANL V
CC
= 0 V; V
CANL
= 5 V 10 170 250
mA
V
CM−peak
Common−mode peak during transition
from dom → rec or rec → dom
Figures 8 and 9 −500 500 mV
V
CM−step
Difference in common−mode between
dominant and recessive state
Figures 8 and 9 −150 150 mV
Power on Reset
PORL
POR level
CANH, CANL, V
ref
in tri−
state below POR level
2.2 3.5 4.7 V
Thermal Shutdown
T
j(sd)
shutdown junction temperature 150 160 180 °C
Timing Characteristics (see Figures 6 and 7)
t
d(TxD−BUSon)
Delay TxD to bus active 40 85 110 ns
t
d(TxD−BUSoff)
Delay TxD to bus inactive 30 60 110 ns
t
d(BUSon−RxD)
Delay bus active to RxD 25 55 110 ns
t
d(BUSoff−RxD)
Delay bus inactive to RxD 65 100 135 ns
t
pd(rec−dom)
Propagation delay TxD to RxD from
recessive to dominant
100 230 ns
t
d(dom−rec)
Propagation delay TxD to RxD from
dominant to recessive
100 245 ns
t
dom(TxD)
TxD dominant time for time out V
TxD
= 0 V 250 450 750
ms
7. Not tested on ATE.
Table 8. Digital Output Characteristics @ V
33
= 2.5 V
(V
CC
= 4.75 to 5.25 V; V
33
= 2.5 V ±5%; T
junc
= −40 to +150°C; R
LT
= 60 W unless specified otherwise.)
Symbol
Parameter Conditions Min. Typ. Max. Unit
Receiver Data Output (pin RxD)
I
oh
HIGH−level output current V
OH
> 0.9 x V
33
−2.6 mA
I
ol
LOW−level output current V
OL
< 0.1 x V
33
4 mA
