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NLSX3012DR2G

P1-P3P4-P6P7-P9P10-P12
© Semiconductor Components Industries, LLC, 2011
September, 2011 − Rev. 2
1 Publication Order Number:
NLSX3012/D
NLSX3012
2-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX3012 is a 2−bit configurable dual−supply bidirectional
level translator without a direction control pin. The I/O V
CC
− and I/O
V
L
−ports are designed to track two different power supply rails, V
CC
and V
L
respectively. The V
CC
supply rail is configurable from 1.3 V
to 4.5 V while the V
L
supply rail is configurable from 0.9 V to (V
CC
− 0.4) V. This allows lower voltage logic signals on the V
L
side to be
translated into higher voltage logic signals on the V
CC
side, and
vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3−state. This significantly reduces the supply
currents from both V
CC
and V
L
. The EN signal is designed to track
V
L
.
Features
• Wide High−Side V
CC
Operating Range: 1.3 V to 4.5 V
Wide Low−Side V
L
Operating Range: 0.9 V to (V
CC
− 0.4) V
• High−Speed with 140 Mb/s Guaranteed Date Rate for V
L
> 1.8 V
• Low Bit−to−Bit Skew
• Overvoltage Tolerant Enable and I/O Pins
• Non−preferential Powerup Sequencing
• Small packaging: UDFN8, SO−8, Micro8
• These are Pb−Free Devices
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
• PC and Laptops
MARKING
DIAGRAMS
http://onsemi.com
UDFN8
MU SUFFIX
CASE 517AJ
1
8
VA = Specific Device Code
M = Date Code
G = Pb−Free Package
VAM
G
Device Package Shipping
†
ORDERING INFORMATION
NLSX3012MUTAG UDFN8
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
8
SO−8
D SUFFIX
CASE 751
A = Assembly Location
Y = Year
W = Work Week
G = Pb−Free Package
SX3012
ALYW G
G
1
8
Micro8
DM SUFFIX
CASE 846A
1
3012
AYW G
G
1
8
NLSX3012DR2G SO−8
(Pb−Free)
2500/Tape & Reel
NLSX3012DMR2G Micro8
(Pb−Free)
4000/Tape & Reel
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
NLSX3012
http://onsemi.com
2
PIN ASSIGNMENTS
Micro8
(Top View)
1
2
3
4
8
7
6
5
1 8
2
3
4
7
6
5
SOIC−8
(Top View)
UDFN8
(Top View)
V
CC
I/O V
CC
1
I/O V
CC
2
EN
V
L
I/O V
L
1
I/O V
L
2
GND
8
7
6
5
1
2
3
4
V
L
V
CC
GND
EN
I/O V
L
1
I/O V
L
2
I/O V
CC
1
I/O V
CC
2
LOGIC DIAGRAM
V
CC
I/O V
CC
1
I/O V
CC
2
EN
V
L
I/O V
L
1
I/O V
L
2
GND
V
CC
I/O V
CC
1
I/O V
CC
2
EN
V
L
I/O V
L
1
I/O V
L
2
GND
PIN ASSIGNMENT
Pins Description
V
CC
V
CC
Input Voltage
V
L
V
L
Input Voltage
GND Ground
EN Output Enable
I/O V
CC
n I/O Port, Referenced to V
CC
I/O V
L
n I/O Port, Referenced to V
L
FUNCTION TABLE
EN Operating Mode
L Hi−Z
H I/O Buses Connected
NLSX3012
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Condition Unit
V
CC
V
CC
Supply Voltage −0.5 to +5.5 V
V
L
V
L
Supply Voltage −0.5 to +5.5 V
I/O V
CC
V
CC
−Referenced DC Input/Output Voltage −0.5 to (V
CC
+ 0.3) V
I/O V
L
V
L
−Referenced DC Input/Output Voltage −0.5 to (V
L
+ 0.3) V
V
EN
Enable Control Pin DC Input Voltage −0.5 to +5.5 V
I
IK
Input Diode Clamp Current −50 V
I
< GND mA
I
OK
Output Diode Clamp Current −50 V
O
< GND mA
I
CC
DC Supply Current Through V
CC
$100 mA
I
L
DC Supply Current Through V
L
$100 mA
I
GND
DC Ground Current Through Ground Pin $100 mA
T
STG
Storage Temperature −65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
V
CC
Supply Voltage 1.3 4.5 V
V
L
V
L
Supply Voltage 0.9 V
CC
− 0.4 V
V
EN
Enable Control Pin Voltage GND 4.5 V
V
IO
Bus Input/Output Voltage I/O V
CC
I/O V
L
GND
GND
4.5
4.5
V
T
A
Operating Temperature Range −40 +85 °C
DI/DV Input Transition Rise or Rate
V
I
, V
IO
from 30% to 70% of V
CC
; V
CC
= 3.3 V $ 0.3 V
0 10 ns
Figure 1. Typical Application Circuit
I/O V
L
1
I/O V
L
2
ENEN
I/O2
I/O1
GND
+1.8 V System
+1.8V +3.6V
+3.6 V System
I/O2
I/O1
GNDGND
NLSX3012
I/O V
CC
1
I/O V
CC
2
V
L
V
CC
Figure 2. Simplified Functional Diagram (1 I/O Line)
(EN = 1)
P
One−Shot
N
One−Shot
P
One−Shot
N
One−Shot
V
L
I/O V
L
I/O V
CC
V
CC
4 kW
4 kW
P1-P3P4-P6P7-P9P10-P12

NLSX3012DR2G

Mfr. #:
Buy NLSX3012DR2G
Manufacturer:
ON Semiconductor
Description:
Translation - Voltage Levels 2 BIT TRANSLATOR
Lifecycle:
New from this manufacturer.
Delivery:
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