ICS9DB403D
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
19
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Printed in USA
TM
Revision History
Rev. Issue Date Description Page #
I 11/26/2008 Updated SMBus table - Byte0:Byte3. 11
J 2/6/2009 Added Industrial temp. specs and orderin
information. Various
K 7/13/2009 Updated general description and block diagram 1
L 10/7/2009
1. Clarified that Vih and Vil values were for Single ended inputs
2. Added separate Idd values for the 9DB403
3. Added Differential Clock input parameters. Various
M 1/27/2011 Updated Termination Figure 4 10
N 5/6/2011
1. Update pin 1 pin-name and pin description from VDD to VDDR. This
highlights that optimal peformance is obtained by treating VDDR as in analog
pin. This is a document update only, there is no silicon change.
Various
P 8/27/2012
Updated Vswing conditions to include "single-ended measurement"
5
Q 9/18/2012
Updated Byte 2, bits 1, 2, 5 and 6 per char review. Outputs can be
programmed with Byte 2 to be Stoppable or Free-Run with DIF_Stop pin, not
the OE pins.
12
R 11/1/2012
Updated Input-to-Output Skew max value (Bypass Mode condition only) from
4500ps to 5000ps per latest characterization data.
7
