Application information STSMIA832
10/25 Doc ID 12174 Rev 5
3.3 Power saving at the inputs
All internal blocks of the input circuitry are shutdown by turning off the bias currents for the
subLVDS receivers. This eliminates the power associated with any dynamic activity on the
input pins. With no pull-up and pull-down resistors, any remaining current drawn by an input
is known as leakage current (I
L
), which ranges from 1 µA to 4 µA typical. But care should be
taken that the driving circuit for the inputs is also switched to a known state and that there
are no transitions on the inputs when the device is in power down mode.
3.4 Switching off digital blocks
To save power, all signals within the device are prevented from switching by resetting all the
digital blocks in the internal circuits. In many designs, a major portion of the total dynamic
power is due to its clock tree, which consists of all the inter-connects that distributes the
clock signal internally. Power drawn varies according to how extensive the tree is. Pulling the
clock input to a static logic level (LOW in this case) is an important way to save power,
especially as the clock frequency is high.
3.5 Disabling the outputs
In the power down mode, to save the power due to transition on output flip flops, the clock
enable (CE) signal for all the flip-flops is used in the design. All the clock transitions are
ignored when the CE signal is inactive and so the output flip flops do not toggle. The CE
signal is activated once again when the registered outputs need to be operating under
normal conditions. All the outputs (including D1-D8) are driven LOW in the power down
state. This reset state is held as long as the device remains in power down mode.
Once having exited the mode, normal operation recommences from the reset state.
3.6 Load capacitance
Power dissipation is proportional to capacitance. The capacitance consists both of internal
and external capacitance. The lumped internal capacitance is associated with the power
dissipated internally by the device and depends on the device characteristics (in
STSMIA832, C
IN
is 4 pF). The external capacitance is associated with power dissipated
outside the device and it is a function of PCB traces loading and other IC loads.
In high frequency operation, it is essential to have equal trace lengths for all the output lines
in order to minimize the skew. A reduced external capacitance leads to reduced current
consumption and also reduced rise time and fall time. The parallel output driving
capacitance in STSMIA832 is 10 pF and the rise time and fall times for the LVTTL parallel
outputs are 2.5 ns maximum.
