MAX5223
Low-Power, Dual, 8-Bit, Voltage Output
Serial DAC in 8-Pin SOT23
_______________________________________________________________________________________ 7
Detailed Description
Analog Section
The MAX5223 contains two 8-bit, voltage output DACs.
The DACs are “inverted” R-2R ladder networks. They
use complementary switches that convert 8-bit digital
inputs into equivalent analog output voltages in propor-
tion to the applied reference voltage.
The MAX5223 has one reference input that is shared
by DAC A and DAC B. The device includes output
buffer amplifiers for both DACs and input logic for sim-
ple microprocessor (µP) and CMOS interfaces. The
power supply range is from +5.5V down to +2.7V.
Reference Input and DAC Output Range
The voltage at REF sets the full-scale output of the
DACs. The input impedance of the REF input is code-
dependent. The lowest value, approximately 8kΩ,
occurs when the input code is 01010101 (55hex). The
typical value of 50MΩ occurs when the input code is
zero.
In shutdown mode, the selected DAC output is set to
zero, while the value stored in the DAC register remains
unchanged. This removes the load from the reference
input to save power. Bringing the MAX5223 out of shut-
down mode restores the DAC output voltage. Since the
input resistance at REF is code-dependent, the DAC’s
reference source should have an output impedance of
no more than 5Ω to meet accuracy specifications and
to avoid crosstalk. The input capacitance at the REF
pin is also code dependent and typically does not
exceed 25pF.
The reference voltage on REF can range anywhere from
GND to V
DD
. See the Output Buffer Amplifier section for
more information. Figure 1 is the DAC simplified circuit
diagram.
Output Buffer Amplifiers
DAC A and DAC B voltage outputs are internally
buffered. The buffer amplifiers have a Rail-to-Rail
®
(GND to V
DD
) output voltage range.
Both DAC output amplifiers can source and sink up to
1mA of current. The amplifiers are unity-gain stable
with a capacitive load of 100pF or smaller. The slew
rate is typically 0.15V/µs.
Shutdown Mode
When programmed to shutdown mode, the outputs of
DAC A and DAC B are passively pulled to GND with a
series 5kΩ resistor. In shutdown mode, the REF input is
high impedance (50MΩ typ) to conserve current drain
from the system reference; therefore, the system refer-
ence does not have to be powered down.
Coming out of shutdown, the DAC outputs return to the
values kept in the registers. The recovery time is equiv-
alent to the DAC settling time.
Serial Interface
An active low chip select (
–
C
—
S
–
) enables the shift register
to receive data from the serial data input. Data is
clocked into the shift register on every rising edge of
the serial clock signal (SCLK). The clock frequency can
be as high as 25MHz.
Data is sent by the most significant bit (MSB) first and
can be transmitted in one 16-bit word. The write cycle
can be segmented when
–
C
—
S
–
is kept active (low) to
allow, for example, two 8-bit wide transfers. After clock-
ing all 16 bits into the input shift register, the rising
edge of
–
C
—
S
–
updates the DAC outputs and the shut-
down status. DACs cannot be simultaneously updated
to different digital values because of their single buffered
structure.
Serial Input Data Format and Control Codes
Table 1 lists the serial input data format and Table 2
lists the programming commands. The 16-bit input
word consists of an 8-bit control byte and an 8-bit data
byte. The 8-bit control byte is not decoded internally.
Every control bit performs one function. Data is clocked
®
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
Figure 1. DAC Simplified Circuit Diagram
