85105I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 20, 20162
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
Number Name Type Description
1 GND Power Power supply ground.
2 CLK_EN Input Pullup
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high. LVTTL /
LVCMOS interface levels.
3 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
4 CLK0 Input Pulldown Non-inverting differential clock input.
5 nCLK0 Input
Pullup/
Pulldown
Inverting differential clock input.
6 CLK1 Input Pulldown Single-ended clock input. LVTTL / LVCMOS interface levels.
7, 8 Q4, nQ4 Output Differential output pair. HCSL interface levels.
9 IREF Input
An external fi xed precision resistor (475Ω) from this pin to ground provides a
reference current used for differential current-mode Qx, nQx outputs.
10, 13, 18 V
DD
Power Positive supply pins.
11, 12 nQ3, Q3 Output Differential output pair. HCSL interface levels.
14, 15 nQ2, Q2 Output Differential output pair. HCSL interface levels.
16, 17 nQ1, Q1 Output Differential output pair. HCSL interface levels.
19, 20 nQ0, Q0 Output Differential output pair. HCSL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
