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AD5320BRTZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD5320
Rev. C | Page 9 of 20
DAC LOADED WITH FFF HEX
DAC LOADED WITH 000 HEX
I
SOURCE/SINK
(mA)
V
OUT
(V)
3
2
1
0
05 10
00934-011
T
A
= 25°C
15
Figure 11. Source and Sink Current Capability with V
DD
= 3 V
5
4
3
2
1
DAC LOADED WITH 000 HEX
DAC LOADED WITH FFF HEX
I
SOURCE/SINK
(mA)
V
OUT
(V)
0
0510
00934-012
15
T
A
= 25°C
Figure 12. Source and Sink Current Capability with V
DD
= 5 V
CODE
I
DD
(µA)
0 800 1600 2400 3200 4000
00934-013
500
400
0
300
200
100
V
DD
= 5V
V
DD
= 3V
Figure 13. Supply Current vs. Code
TEMPERATURE °C
I
DD
(µA)
300
200
150
50
0
–40 0 40 80 120
00934-014
V
DD
= 5V
Figure 14. Supply Current vs. Temperature
V
DD
(V)
2.7 3.2 3.73.7 4.2 4.7 5
00934-015
300
250
200
150
100
50
0
I
DD
(µA)
T
A
= 25°C
Figure 15. Supply Current vs. Supply Voltage
2.7 3.2 3.7 4.7 5.24.2
00934-016
1.0
0.9
0
0.4
0.3
0.2
0.1
0.8
0.6
0.7
0.5
–40°C
CONDITION
THREE-STATE
V
DD
(V)
I
DD
(µA)
+25°C
+105°C
Figure 16. Power-Down Current vs. Supply Voltage
AD5320
Rev. C | Page 10 of 20
T
A
= 25°C
V
DD
= 5V
V
LOGIC
(V)
I
DD
(µA)
800
600
400
200
0
054321
00934-017
V
DD
= 3V
Figure 17. Supply Current vs. Logic Input Voltage
V
OUT
CLK
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
CH2
CH1
00934-018
V
DD
= 5V
FULL-SCALE CODE CHANGE
000 HEX – FFF HEX
T
A
= 25°C
OUTPUT LOADED WITH
2kΩ AND 200pF TO GND
Figure 18. Full-Scale Settling Time
V
OUT
CLK
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
00934-019
C
H1
C
H2
V
DD
= 5V
HALF-SCALE CODE CHANGE
400 HEX – C00 HEX
T
A
= 25°C
OUTPUT LOADED WITH
2kΩ AND 200pF TO GND
Figure 19. Half-Scale Settling Time
CH1
CH2
CH1 1V, CH 2 1V, TIME BASE = 20µs/DIV
00934-020
2kΩ LOAD TO V
DD
V
DD
V
OUT
Figure 20. Power-On Reset to 0 V
CH1 1V, CH2 5V, TIME BASE = 5µs/DIV
00934-021
CH2
CH1
CLK
V
OUT
V
DD
= 5V
Figure 21. Exiting Power-Down (800 Hex Loaded)
LOADED WITH 2kΩ
AND 200pF TO GND
CODE CHANGE:
800 HEX TO 7FF HEX
500ns/DIV
V
OUT
(V)
00934-022
2.54
2.52
2.50
2.48
2.46
2.56
Figure 22. Digital-to-Analog Glitch Impulse
AD5320
Rev. C | Page 11 of 20
THEORY OF OPERATION
D/A SECTION
The AD5320 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Because there is no reference input pin, the
power supply (V
DD
) acts as the reference. Figure 23 shows a
block diagram of the DAC architecture.
V
DD
V
OUT
GND
RESISTOR
STRING
REF (+)
REF (–)
OUTPUT
AMPLIFIER
DAC REGISTER
00934-023
Figure 23. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
⎟
⎠
⎞
⎜
⎝
⎛
×=
4096
D
VV
DD
OUT
where
D = decimal equivalent of the binary code that is loaded
to the DAC register; it can range from 0 to 4095.
RESISTOR STRING
The resistor string section is shown in Figure 24. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
R
R
R
R
R
TO OUTPUT
AMPLIFIER
00934-024
Figure 24. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output that gives an output range of 0 V to V
DD
. It
is capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in
Figure 11 and Figure 12. The slew rate is 1 V/μs
with a half-scale settling time of 8 μs with the output unloaded.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD5320BRTZ-REEL

Mfr. #:
Buy AD5320BRTZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12 Bit Vout 8uS
Lifecycle:
New from this manufacturer.
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