308RLF Datasheet 308RLF, 308RLFT, 308RILF | P1-P3

DATASHEET

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER ICS308

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 1

ICS308 REV L 051310

Description

The ICS308 is a versatile serially programmable, quad

PLL clock source. The ICS308 can generate any

frequency from 250 kHz to 200 MHz, and up to 6

different output frequencies simultaneously. The

outputs can be reprogrammed on the fly, and will lock to

a new frequency in 10 ms or less. Smooth transitions

(in which the clock duty cycle remains roughly 50%) are

guaranteed if the output divider is not changed.

The device includes a PDTS

pin which tri-states the

output clocks and powers down the entire chip.

The ICS308 default for non-programmed start-up are

buffered reference clock outputs on all clock output

pins.

Features

• Packaged in 20-pin SSOP (QSOP) – Pb-free, RoHS

compliant

• Operating voltage of 3.3 V

• Highly accurate frequency generation

• M/N Multiplier PLL: M = 1..2048, N = 1..1024

• Serially programmable: user determines the output

frequency via a 3-wire interface

• Eliminates need for custom quartz oscillators

• Input crystal frequency of 5 - 27 MHz

•Optional programmable on-chip crystal capacitors

• Output clock frequencies up to 200 MHz

• Reference clock output

• Power down tri-state mode

• Very low jitter

Block Diagram

Crystal

Oscillator

GND

VDD

PDTS

PLL2

PLL3

Divide

Logic

and

Output

Enable

Control

SCLK

DATA

CLK1

CLK9

CLK8

CLK7

CLK6

CLK5

CLK4

CLK3

CLK2

PLL4

PLL1

Crystal or

clock input

External capacitors are

required with a crystal input.

X1/ICLK

STROBE

ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 2

ICS308 REV L 051310

Pin Assignment

Pin Descriptions

DATA STROBE

X1/ICLK

SCLK

CLK9

PDTS

VDD

GND

VDD

GND

CLK1

CLK5

CLK2

CLK6

CLK3

CLK7

CLK4

CLK8

20 pin (150 mil) SSOP (QSOP)

Number

Name

Type

Pin Description

1 DATA Input Serial data input.

2 X2 XO Crystal Output. Connect this pin to a crystal. Float for clock input.

3 X1/ICLK XI Connect this pin to a crystal or external clock input.

4 CLK9 Output Output clock 9. Default of Reference frequency output when unprogrammed.

5 VDD Power Connect to +3.3 V.

6 GND Power Connect to Ground.

7 CLK1 Output Output clock 1. Default of Reference frequency output when unprogrammed.

8 CLK2 Output Output clock 2. Default of Reference frequency output when unprogrammed.

9 CLK3 Output Output clock 3. Default of Reference frequency output when unprogrammed.

10 CLK4 Output Output clock 4. Default of Reference frequency output when unprogrammed.

11 CLK8 Output Output clock 8. Default of Reference frequency output when unprogrammed.

12 CLK7 Output Output clock 7. Default of Reference frequency output when unprogrammed.

13 CLK6 Output Output clock 6. Default of Reference frequency output when unprogrammed.

14 CLK5 Output Output clock 5. Default of Reference frequency output when unprogrammed.

15 GND Power Connect to Ground.

16 VDD Power Connect to +3.3 V.

17 VDD Power Connect to +3.3 V.

18 PDTS

Input Powers down entire chip, tri-states all outputs when low. Internal pull-up.

19 SCLK Input Serial Shift register clock. See timing diagram.

20 STROBE Input Strobe to load data. See timing diagram. Use external 250 kOhm pull-up.

ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER

IDT™ / ICS™

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 3

ICS308 REV L 051310

Configuring the ICS308

Initial State: The ICS308 may be configured to have up to nine frequency outputs, utilizing the four

on-board PLLs. Unprogrammed, the part has the following outputs, related to the reference input clock:

The STROBE pin must have an external 250 kOhm pull-up resistor to achieve the Initial State.

The input crystal range for the ICS308 is 5 MHz to 27 MHz.

The ICS308 can be programmed to set the output functions and frequencies. 160 data bits generated by

the VersaClock

software are written in DATA pin in this order: MSB (left most bit) first.

As show in Figure 2, after these 160 bits are clocked into the ICS308, taking STROBE high will send this

data to the internal hatch and the CLK output will lock within 10 ms.

Note: STROBE utilizes a transparent latch that is latched when in the high state. If STROBE is in the high

state and SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will

change accordingly. Although this will not damage the ICS308, it is recommended that STROBE be kept

low while DATA is being clocked into the ICS308 in order to avoid unintended changes on the output clocks.

All outputs may be turned off during initialization by bringing the PDTS

pin to Ground. When PDTS is

brought high, after the Strobe pin in brought high, the programmed output frequencies will be available.

AC Parameters for Writing to the ICS308

Default Outputs

Output Frequency

Clock 1-9 (Pins 4, 10 - 14) Reference Output

Parameter Condition Min. Max. Units

SETUP

Setup time 10 ns

HOLD

Hold time after SCLK 10 ns

Data wait time 10 ns

Strobe pulse width 40 ns

SCLK Frequency 30 MHz

DATA

hold

setup

SCLK

STROBE

Figure 2. Timing Diagram for Programming the ICS308

Bit160 Bit2 Bit1

Bit3

Bit159 Bit158

P1-P3 P4-P6 P7-P9

308RLF

Mfr. #:

Buy 308RLF

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK

Lifecycle:

New from this manufacturer.

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