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Supply Voltage (V)
0 5 10 15 20 25 30 35 40
Output Resistance (Ω)
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
High-State Output Resistance @ -10mA
vs. Supply Voltage
Temperature (ºC)
-40 -20 0 20 40 60 80 100 120 140
Output Sink Current (A)
16
17
18
19
20
21
22
23
24
Output Sink Current
vs. Temperature
(C
L
=330nF, V
CC
=18V)
Temperature (ºC)
-40 -20 0 20 40 60 80 100 120 140
Output Source Current (A)
-10
-12
-14
-16
-18
-20
-22
Output Source Current
vs. Temperature
(C
L
=330nF, V
CC
=18V)
Supply Voltage (V)
0 5 10 15 20 25 30 35 40
Output Resistance (Ω)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Low-State Output Resistance @ +10mA
vs. Supply Voltage
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5 Manufacturing Information
5.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classifies its plastic encapsulated devices for moisture sensitivity according to the latest
version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation.
We test all of our products to the maximum conditions set forth in the standard, and guarantee proper
operation of our devices when handled according to the limitations and information in that standard as well as to any
limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled
according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
5.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.
5.3 Soldering Profile
Provided in the table below is the Classification Temperature (T
C
) of this product and the maximum dwell time the
body temperature of this device may be (T
C
- 5)ºC or greater. The classification temperature sets the Maximum Body
Temperature allowed for this device during lead-free reflow processes. For through-hole devices, and any other
processes, the guidelines of J-STD-020 must be observed.
5.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. Board washing to reduce or
remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to
prevent damage to the device. These precautions include but are not limited to: using a low pressure wash and
providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing
process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature
and duration necessary to remove the moisture trapped within the package is the responsibility of the user
(assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not be
used. Additionally, the device must not be exposed to flux or solvents that are Chlorine- or Fluorine-based.
Device Moisture Sensitivity Level (MSL) Classification
IXD_614SI / IXD_614PI /IXD_614CI MSL 1
IXD_614YI MSL 3
Device
Classification Temperature (T
C
) Dwell Time (t
p
)
Max Reflow Cycles
IXD_614CI 245°C 30 seconds 1
IXD_614YI 245°C 30 seconds 3
IXD_614PI 250°C 30 seconds 3
IXD_614SI 260°C 30 seconds 3
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5.5 Mechanical Dimensions
5.5.1 SI (8-Pin Power SOIC with Exposed Metal Back)
Note:
The exposed metal pad on the back of the SI package should be connected to GND. It is not suitable for
carrying current.
5.5.2 SI Package Tape & Reel Information
Recommended PCB Land Pattern
Dimensions
mm
(inches)
1.346 ± 0.076
(0.053 ± 0.003)
0.051 MIN - 0.254 MAX
(0.002 MIN - 0.010 MAX)
4.928 ± 0.254
(0.194 ± 0.010)
Pin 1
0.406 ± 0.076
(0.016 ± 0.003)
5.994 ± 0.254
(0.236 ± 0.010)
3.937 ± 0.254
(0.155 ± 0.010)
1.270 REF
(0.050)
0.762 ± 0.254
(0.030 ± 0.010)
2.540 ± 0.254
(0.100 ± 0.010)
3.556 ± 0.254
(0.140 ±0.010)
1.27
(0.050)
5.40
(0.209)
1.55
(0.061)
0.60
(0.024)
2.75
(0.108)
3.80
(0.150)
Dimensions
mm
(inches)
NOTE:
Tape dimensions not shown comply with JEDEC Standard EIA-481-2
Embossment
Embossed Carrier
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
330.2 DIA.
(13.00 DIA.)
K
0
= 2.10
(0.083)
W=12.00
(0.472)
B
0
=5.30
(0.209)
User Direction of Feed
A
0
=6.50
(0.256)
P=8.00
(0.315)

IXDD614CI

Mfr. #:
Manufacturer:
IXYS Integrated Circuits
Description:
Gate Drivers 14-Ampere Low-Side Ultrafast MOSFET
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union