MC74VHC259MELG

MC74VHC259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHC259 is an 8–bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation similar to
equivalent Bipolar Schottky TTL devices while maintaining CMOS low
power dissipation.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in the
mode selection table.. In the addressable latch mode, the data on Data In
is written into the addressed latch. The addressed latch follows the data
input with all non–addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state and are
unaffected by the Data or Address inputs. In the one–of–eight decoding
or demultiplexing mode, the addressed output follows the state of Data In
with all other outputs in the LOW state. In the Reset mode, all outputs are
LOW and unaffected by the address and data inputs. When operating the
VHC259 as an addressable latch, changing more than one bit of the
address could impose a transient wrong address. Therefore, this should
only be done while in the memory mode.
The MC74VHC259 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
MC74VHC259 to be used to interface 5 V circuits to 3 V circuits.
High Speed: t
PD
= 7.6 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 2 µA (Max) at T
A
= 25°C
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
CMOS–Compatible Outputs: V
OH
> 0.8 V
CC
; V
OL
< 0.1 V
CC
@Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V
Figure 1. Pin Assignment
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
A0
A2
A1
GND
DATA IN
ENABLE
RESET
V
CC
Q0
Q1
Q3
Q2
Q7
Q6
Q5
Q4
Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 2
1 Publication Order Number:
MC74VHC259/D
http://onsemi.com
Device Package Shipping
ORDERING INFORMATION
MC74VHC259D SOIC–16 48 Units/Rail
MC74VHC259DR2 SOIC–16
2500 Units/Reel
SOIC–16
D SUFFIX
CASE 751B
TSSOP–16
DT SUFFIX
CASE 948F
MARKING DIAGRAMS
1
8
9
16
1
8
16 9
VHC259
AWLYYWW
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
VHC259
AWLYWW
MC74VHC259DT TSSOP–16 96 Units/Rail
MC74VHC259M
SOIC
EIAJ–16
50 Units/Rail
MC74VHC259DTR2 TSSOP–16 2500 Units/Reel
SOIC EIAJ–16
M SUFFIX
CASE 966
1
16 9
8
VHC259
ALYW
MC74VHC259MEL
SOIC
EIAJ–16
2000 Units/Reel
MC74VHC259
http://onsemi.com
2
LATCH SELECTION TABLE
Address Inputs
Latch
Addressed
L
H
L
H
H
L
H
CB
A
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
5
6
7
8
10
11
12
15
14
13
3
2
1
A0
A1
A2
2
1
4
BIN/OCT
1
0
2
4
3
5
6
7
EN
A0
A1
A2
0
2
DMUX
1
0
2
4
3
5
6
7
G
0
7
ID
R
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
15
14
13
3
2
1
EN
ID
R
4
5
6
7
8
10
11
12
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q7
4
3
2
1
A0
A1
A2
NONINVERTING
OUTPUTS
ADDRESS
INPUTS
Figure 2. Logic Diagram
DATA IN
13
15
14
RESET
ENABLE
5
6
7
9
10
11
12
Q6
Q5
Q4
Q3
Q2
Q1
Q0
PIN 16 = V
CC
PIN 8 = GND
Figure 3. IEC Logic Symbol
MODE SELECTION TABLE
Enable Reset Mode
L
H
L
HL
H
L
H Addressable Latch
Memory
8–Line Demultiplexer
Reset
MC74VHC259
http://onsemi.com
3
D
Figure 4. Expanded Logic Diagram
DATA INPUT
13 4
Q0
D
5
Q1
D
6
Q2
D
7
Q3
D
9
Q4
D
10
Q5
D
11
Q6
D
12
Q7
3 TO 8
DECODER
ENABLE
14
RESET
15
A0
A1
A2
ADDRESS
INPUTS

MC74VHC259MELG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC LATCH/DCODE 8BIT ADD 16SOEIAJ
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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