AD876JSTZ Datasheet AD876JSTZ, AD876JR, AD876JR-REEL | P10-P12

AD876

REV. B

–9–

Figure 16 shows the equivalent input structure for the AD876

reference pins. There is approximately 5 Ω of resistance between

both the REFTF and REFBT pins and the reference ladder. If

the force-sense connections are not used, the voltage drop

across the 5 Ω resistors will result in a reduced voltage appear-

ing across the ladder resistance. This reduces the input span of

the converter. Applying a slightly larger span between the REFTF

and REFBF pins compensates this error. Note that the tem-

perature coefficients of the 5 Ω resistors are 1350 ppm. The

user should consider the effects of temperature when not using

a force-sense reference configuration.

AD876

REFTF

REFTS

REFBS

REFBF

DACS

C (V

)

CLK

250V

LADDER

Figure 16. AD876 Equivalent Reference Structure

Do not connect the REFTS and REFBS pins in configurations

that do not use a force-sense reference. Connecting the force

and sense lines together allows current to flow in the sense lines.

Any current allowed to flow through these lines must be negligi-

bly small. Current flow causes voltage drops across the resis-

tance in the sense lines. Because the internal D/As of the

AD876 tap different points along the sense lines, each D/A

would receive a slightly different reference voltage if current

were flowing in these wires. To avoid this undesirable condition,

leave the sense lines unconnected. Any current allowed to flow

through these lines must be negligibly small (<100 µA).

The voltage drop across the internal resistor ladder determines

the input span of the AD876. The driving voltages required at

the V1 and V2 points are respectively +4 V and +2 V. Calculate

the full-scale input span from the equation

Input Span (V )= REFTS – REFBS

This results in a full-scale input span of approximately +2 V

when REFTS = +4 V and REFBS = +2 V In order to maintain

the requisite 2 V drop across the internal ladder, the external

reference must be capable of providing approximately 8.0 mA.

The user has flexibility in determining both the full-scale span of

the analog input and where to center this voltage. Figure 17

shows the range over which the AD876 can operate without

degrading the typical performance.

2.5

3.0

3.5

4.0

4.5

1.0 1.5 2.0 2.5 3.0

REFBF, REFBS

REFTF, REFTS

(1.6, 4.5)

(2.5, 4.5)

(1.6, 3.5)

(2.5, 3.5)

Figure 17. AD876 Reference Ranges

While the previous issues address the dc aspects of the AD876

reference, the user must also be aware of the dynamic imped-

ance changes associated with the reference inputs. The simpli-

fied diagram of Figure 16 shows that the reference pins connect

to a capacitor for one-half of the clock period. The size of the

capacitor is a function of the analog input voltage.

The external reference must be able to maintain a low imped-

ance over all frequencies of interest in order to provide the charge

required by the capacitance. By supplying the requisite charge,

the reference voltages will be relatively constant and perfor-

mance will not degrade. For some reference configurations,

voltage transients will be present on the reference lines; this

is particularly true during the falling edge of CLK. It is impor-

tant that the reference recovers from the transients and settles to

the desired level of accuracy prior to the rising edges of CLK.

There are several reference configurations suitable for the

AD876 depending on the application, desired level of accuracy,

and cost trade-offs. The simplest configuration, shown in Fig-

ure 18, utilizes a resistor string to generate the reference volt-

ages from the converter’s analog power supply. The 0.1 µF

bypass capacitors effectively reduce high-frequency transients.

The 10 µF capacitors act to reduce the impedances at the

REFTF and REFBF pins at lower frequencies. As input fre-

quencies approach dc, the capacitors become ineffective, and

small voltage deviations will appear across the biasing resistors.

This application can maintain 10-bit accuracy for input frequen-

cies above approximately 200 Hz. 8-bit applications can use this

circuit for input frequencies above approximately 50 Hz.

+5V

AD876

10mF

0.1mF

10mF

0.1mF

250V (61%)

140V (61%)

250V

(615%)

REFTS

REFTF

REFBF

REFBS

NC = NO CONNECT

Figure 18. Low Cost Reference Circuit

This reference configuration provides the lowest cost but has

several disadvantages. These disadvantages include poor dc

power supply rejection and poor accuracy due to the variability

of the internal and external resistors.

The AD876 offers force-sense reference connections to elimi-

nate the voltage drops associated with the internal connections

to the reference ladder. Figure 19 shows a suggested circuit

using an AD826 dual, high speed op amp. This configuration

uses 3.6 V and 1.6 V reference voltages for REFT and REFB,

respectively. The connections shown in Figure 19 configure the

op amps as voltage followers.

REV. B–10–

AD876

+5V

1/2

AD826

1/2

AD826

REFT

REFB

REFTS

REFTF

REFBS

REFBF

0.1mF

Figure 19. Kelvin Connected Reference Using the AD826

By connecting the op amp feedback through the sense connec-

tions of the AD876, the outputs of the op amps automatically

adjust to compensate for the voltage drops that occur within

the converter. The AD826 has the advantage of being able to

maintain stability while driving unlimited capacitive loads. As a

result, 0.1 µF capacitors C1, C2, and C3 can connect directly

to the outputs of the op amps. These decoupling capacitors

reduce high frequency transients. Capacitors C4 and C5 shunt

across the internal resistors of the force sense connections and

prevent instability.

This configuration provides excellent performance and a mini-

mal number of components. The circuit also offers the advan-

tage of operating from a single +5 V supply. While alternative

op amps may also be suitable, consider the stability of these op

amps while driving capacitive loads.

The circuit shown in Figure 20 allows a wider selection of op

amps when compared with the previous configuration. An

AD876

1/2

OP-295

10mF 0.1mF

REFT

REFTS

REFTF

47nF

20kV

10V

1/2

OP-295

10mF

0.1mF

REFB

REFBS

REFBF

47nF

20kV

10V

22mF

Figure 20. Kelvin Connected Reference Using the OP295

OP295 dual, single-supply op amp provides stable 3.6 V and

1.6 V reference voltages. The AD822 dual op amp is also suit-

able for single-supply applications. Each half of the OP295 is

compensated to drive the 10 µF and 0.1 µF decoupling capaci-

tors at the REFTF and REFBF pins and maintain stability.

Like any high resolution converter, the layout and decoupling of

the reference is critical. The actual voltage digitized by the

AD876 is relative to the reference voltages. In Figure 21, for

example, the reference return and the bypass capacitors are

connected to the shield of the incoming analog signal. Distur-

bances in the ground of the analog input, that will be common-

mode to the REFT, REFB, and AIN pins because of the

common ground, are effectively removed by the AD876’s high

common-mode rejection.

High frequency noise sources, V

and V

, are shunted to

ground by decoupling capacitors. Any voltage drops between

the analog input ground and the reference bypassing points will

be treated as input signals by the converter via the reference

inputs. Consequently, the reference decoupling capacitors

should be connected to the same analog ground point used to

define the analog input voltage. (For further suggestions, see

the “Grounding and Layout Rules” section of the data sheet.)

REFTF

REFBF

AIN

AD876

Figure 21. Recommended Bypassing for the Reference

Inputs

CLOCK INPUT

The AD876 clock input is buffered internally with an inverter

powered from the DRV

pin. This feature allows the AD876

to accommodate either +5 V or +3.3 V CMOS logic input sig-

nal swings with the input threshold for the CLK pin nominally

at DRV

/2.

The AD876’s pipelined architecture operates on both rising and

falling edges of the input clock. To minimize duty cycle varia-

tions the recommended logic family to drive the clock input is

high speed or advanced CMOS (HC/HCT, AC/ACT) logic.

CMOS logic provides both symmetrical voltage threshold levels

and sufficient rise and fall times to support 20 MSPS operation.

The AD876 is designed to support a conversion rate of 20 MSPS;

running the part at slightly faster clock rates may be possible,

although at reduced performance levels. Conversely, some

slight performance improvements might be realized by clocking

the AD876 at slower clock rates.

The power dissipated by the correction logic and output buffers

is largely proportional to the clock frequency; running at reduced

clock rates provides a reduction in power consumption. Figure

8 illustrates this trade-off.

DIGITAL INPUTS AND OUTPUTS

Each of the AD876 digital control inputs, THREE-STATE and

STBY, has an input buffer powered from the DRV

supply

pins. With DRV

set to +5 V, all digital inputs readily inter-

face with +5 V CMOS logic. For interfacing with lower voltage

CMOS logic, DRV

can be set to 3.3 V, effectively lowering

the nominal input threshold of all digital inputs to 3.3 V/2 =

1.65 V.

The format of the digital output is straight binary. Table I shows

the output format for the case where REFTS = 4 V and REFBS

= 2 V.

AD876

REV. B

–11–

For DRV

= 5 V, the AD876 output signal swing is compat-

ible with both high speed CMOS and TTL logic families. For

TTL, the AD876 on-chip, output drivers were designed to

support several of the high speed TTL families (F, AS, S). For

applications where the clock rate is below 20 MSPS, other TTL

families may be appropriate. For interfacing with lower voltage

CMOS logic, the AD876 sustains 20 MSPS operation with

DRV

= 3.3 V. In all cases, check your logic family data

sheets for compatibility with the AD876 Digital Specification

table.

THREE-STATE OUTPUTS

The digital outputs of the AD876 can be placed in a high im-

pedance state by setting the THREE-STATE pin to HIGH.

This feature is provided to facilitate in-circuit testing or

evaluation. Note that this function is not intended for enabling/

disabling the ADC outputs from a bus at 20 MSPS. Also, to

avoid corruption of the sampled analog signal during conversion

(3.5 clock cycles), it is highly recommended that the AD876

outputs be enabled on the bus prior to the first sampling. For

the purpose of budgetary timing, the maximum access and float

delay times (t

, t

shown in Figure 15) for the AD876 are

150 ns.

THREE-STATE

ACTIVE

HIGH IMPEDANCE

D0–D9

Figure 22. High-Impedance Output Timing Diagram

Table I. Output Data Format

Approx. THREE- DATA

AIN (V) STATE D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

>4 0 1111111111

4 0 1111111111

3 0 1000000000

2 0 0000000000

<2 0 0000000000

X 1 ZZZZZZZZZZ

A low power mode feature is provided such that for STBY =

HIGH and the clock disabled, the static power of the AD876

will drop below 50 mW.

GROUNDING AND LAYOUT RULES

As is the case for any high performance device, proper ground-

ing and layout techniques are essential in achieving optimal

performance. The analog and digital grounds on the AD876

have been separated to optimize the management of return

currents in a system. It is recommended that a printed circuit

board (PCB) of at least 4 layers employing a ground plane and

power planes be used with the AD876. The use of ground and

power planes offers distinct advantages:

1. The minimization of the loop area encompassed by a signal

and its return path.

2. The minimization of the impedance associated with ground

and power paths.

3. The inherent distributed capacitor formed by the power

plane, PCB insulation, and ground plane.

These characteristics result in both a reduction of electro-

magnetic interference (EMI) and an overall improvement in

performance.

It is important to design a layout which prevents noise from

coupling onto the input signal. Digital signals should not be run

in parallel with the input signal traces and should be routed

away from the input circuitry. Separate analog and digital

grounds should be joined together directly under the AD876. A

solid ground plane under the AD876 is also acceptable if the

power and ground return currents are managed carefully. A

general rule of thumb for mixed signal layouts dictates that the

return currents from digital circuitry should not pass through

critical analog circuitry. For further layout suggestions, see the

AD876 Evaluation Board data sheet.

DIGITAL OUTPUTS

Each of the on-chip buffers for the AD876 output bits (D0–D9)

is powered from the DRV

supply pins, separate from AV

. The output drivers are sized to handle a variety of logic

families while minimizing the amount of glitch energy gener-

ated. In all cases, a fan-out of one is recommended to keep the

capacitive load on the output data bits below the specified 20 pF

level.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD876JSTZ

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 10-Bit 20MSPS 160mW CMOS

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AD876JSTZ

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