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MC74VHC1G50DFT2

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2006
March, 2006 -- Rev. 12
1 Publication Order Number:
MC74VHC1G50/D
MC74VHC1G50
Buffer
The MC74VHC1G50 is an advanced high speed CMOS buf fer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output.
The MC74VHC1G50 input structure provi des protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G50 to be used to interface 5.0 V circuits to 3.0 V
circuits.
• High Speed: t
PD
= 3.5 ns (Typ) at V
CC
=5V
• Low Power Dissipation: I
CC
=1mA(Max)atT
A
=25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation D elays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FET = 104; Equivalent Gate = 26
• These devices are available in Pb--free package(s). Specifications herein
apply to both standard and Pb--free devices. Please see our website at
www.onsemi.com for specific Pb--free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
Figure 1. Pinout (Top View)
V
CC
NC
IN A
OUT Y
GND
IN A
OUT Y
1
Figure 2. Logic Symbol
1
2
3
5
4
FUNCTION TABLE
See detailed ordering and shipping informationinthepackage
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
L
H
A Input Y Output
L
H
SC--88A / SOT--353/SC--70
DF SUFFIX
CASE 419A
Pin 1
d = Date Code
VR
d
TSOP--5/SOT--23/SC--59
DT SUFFIX
CASE 483
Pin 1
d = Date Code
VR
d
MARKING
DIAGRAMS
PIN ASSIGNMENT
1
2
3GND
NC
IN A
4
5V
CC
OUT Y
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MC74VHC1G50
http://onsemi.com
2
MAXIMUM RATINGS (Note 1)
Symbol
Characteristics Value Unit
V
CC
DC Supply Voltage --0.5to+7.0 V
V
IN
DC Input Voltage --0.5to+7.0 V
V
OUT
DC Output Voltage V
CC
=0
High or Low State
--0.5to7.0
--0.5toV
CC
+0.5
V
I
IK
Input Diode Current -- 2 0 mA
I
OK
Output Diode Current V
OUT
< GND; V
OUT
>V
CC
+20 mA
I
OUT
DC Output Current, per Pin +25 mA
I
CC
DC Supply Current, V
CC
and GND +50 mA
P
D
Power dissipation in still air SC--88A, TSOP--5 200 mW
θ
JA
Thermal resistance SC--88A, TSOP--5 333 °C/W
T
L
Lead temperature, 1 mm from case for 10 s 260 °C
T
J
Junction temperature under bias +150 °C
T
stg
Storage temperature --65 to +150 °C
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
N/A
V
I
Latch--Up
Latch--Up Performance Above V
CC
and Below GND at 125°C(Note5) ±500 mA
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
2. Tested to EIA/JESD22--A114--A
3. Tested to EIA/JESD22--A115--A
4. Tested to JESD22--C101--A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
IN
DC Input Voltage 0.0 5.5 V
V
OUT
DC Output Voltage 0.0 V
CC
V
T
A
Operating Temperature Range -- 5 5 +125 °C
t
r
,t
f
Input Rise and Fall Time V
CC
=3.3V± 0.3 V
V
CC
=5.0V± 0.5 V
0
0
100
20
ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100
1000
TIME, YEARS
NORMALIZED FAILURE RATE
T
J
=80
C°
T
J
=90
C°
T
J
= 100 C°
T
J
=110 C°
T
J
= 130 C°
T
J
= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time
Junction Temperature
MC74VHC1G50
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3
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
CC
(V)
T
A
=25°C T
A
≤ 85°C -- 5 5 ≤ T
A
≤ 125°C
Unit
Min Typ Max Min Max Min Max
V
IH
Minimum High--Level
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
V
IL
Maximum Low--Level
Input Voltage
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
V
OH
Minimum High--Level
Output Voltage
V
IN
=V
IH
or V
IL
V
IN
=V
IH
or V
IL
I
OH
=--50mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
V
IN
=V
IH
or V
IL
I
OH
=--4mA
I
OH
=--8mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
V
OL
Maximum Low--Level
Output Voltage
V
IN
=V
IH
or V
IL
V
IN
=V
IH
or V
IL
I
OL
=50mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
=V
IH
or V
IL
I
OL
=4mA
I
OL
=8mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
I
IN
Maximum Input
Leakage Current
V
IN
=5.5VorGND 0to
5.5
±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent
Supply Current
V
IN
=V
CC
or GND 5.5 1.0 20 40
mA
AC ELECTRICAL CHARACTERISTICS C
load
= 50 pF, Input t
r
=t
f
=3.0ns
Symbol Parameter Test Conditions
T
A
=25°C T
A
≤ 85°C -- 5 5 ≤ T
A
≤ 125°C
Unit
Min Typ Max Min Max Min Max
t
PLH
,
t
PHL
Maximum Propaga-
tion Delay,
Input A to
Y
V
CC
=3.3± 0.3 V C
L
=15pF
C
L
=50pF
4.5
6.4
7.1
10.6
8.5
12.0
10.0
14.5
ns
V
CC
=5.0± 0.5 V C
L
=15pF
C
L
=50pF
3.5
4.5
5.5
7.5
6.5
8.5
8.0
10.0
C
IN
Maximum Input Ca-
pacitance
4 10 10 10 pF
C
PD
Power Dissipation Capacitance (Note 6)
Typical @ 25 °C, V
CC
=5.0V
pF
8.0
6. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
=C
PD
¯ V
CC
¯ f
in
+I
CC
.C
PD
is used to determine the no--load dynamic
power consumption; P
D
=C
PD
¯ V
CC
2
¯ f
in
+I
CC
¯ V
CC
.
P1-P3P4-P6P7-P8

MC74VHC1G50DFT2

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Buy MC74VHC1G50DFT2
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 2-5.5V Single
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