LV5813TT-TE-L-H Datasheet LV5813TT-TE-L-H | P4-P6

LV5813TT

Block Diagram and Sample Application Circuit (3.3V output)

TSD

Vref

0.8V

Internal

Regulator

Internal

Regulator

Pin short

protection

BOOT

0.25

FB

COMP

SS

EN

+-

+

-

+

-

GND

V

IN

V

IN

L1 : NR8040T100M [TAIYO YUDEN]

D1 : SBM30-03 [SANYO]

C8 C2 : GRM31CB31E106KA75 [MURATA]

C5 C9 : C2012JB0J106M [TDK]

C : Ceramic Capacitor

L1 = 10μH

C2 C8 = 10μF/25V × 2

C6 =

0.015μF

R2 =

6.8kΩ

R3 =

10kΩ

R1 =

27kΩ

R10 =

4.7kΩ

C3 =

3300pF

C1 =

0.022μF

Rb =

100Ω

V

OUT

SW

OSC

370kHz

UVLO

Output

logic

Pre-Drive

C5 C9 =

10μF/6.3V × 3

D1

H : ON

L : OFF

Error

Amp

PWM

Comparator

Slope

comp

Pin Function

Pin No. Pin name Description Equivalent Circuit

1 BOOT Upper MOS transistor boot strap capacitance

connection pin

Connect the boot capacitan

ce of about 0.022μF

between SW pins

To protect the SW pin’s absolute maximum rating,

to e

nsure stable operation, and to eliminate

noise, the boot capacitance serial resistance

(about 100Ω) Rb proves effective.

Short protection

circuit

SW

BOOT

Output MOS

V

IN

2 V

IN

Input voltage pin.

Connect substantially large (10μF 2

parameters

or more) capacitance between this pin and GND.

See BOOT

3 SW Power switch pin.

Connect the output LC fil

ter. Connect the above

capacitance between this pin and BOOT pin.

See BOOT

4 GND Ground pin.

-

Continued on next page.

No.A1761-4/9

LV5813TT

Continued from preceding page.

Pin No. Pin name Description Equivalent Circuit

5 FB Feedback pin

Sets the output voltage by means of split resistor

in the

section of the output voltage V

OUT

- FB -

GND. V

OUT

setting is made as calculated

below :

V

OUT

=

Vref × {1+

(R1 + R10)

R3

}

Vref = 0.8V

Example : 3.3V output voltage

(See block diagram and sample application

cir

cuit)

V

OUT

= 0.

8 × {1+

(27k + 4.3k)

10k

}

= 3.304V

5μA

Internal regulation

line

V

IN

FB

SS

VREF

0.8V

6 COMP Phase compensation pin

Connects with the phase compensation external

cap

acitance and resistance of DC/DC converter

close loop.

Internal regulation line

V

IN

COMP

Short

protection

circuit

7 EN Enable pin

Converter enabled when set to the HIGH voltage

and di

sabled when connected to GND.

V

IN

EN

8 SS Soft start pin

Set the soft start time by means of the built-in 5μA

sour

ce voltage and external soft start capacity

Css can be set as follows :

C6 = 5μA ×

Ts

s

Vref

Where, Tss is soft start time and Vref is the

referen

ce voltage.

Example : 2.4ms soft start time achieved

Css =

5μA ×

2.4ms

0.8V

= 0.015μF

No.A1761-5/9

LV5813TT

Reference data (1)

I

CC

1 -- Ta

70

75

90

95

100

105

80

85

2.1

2.2

2.0

110

--40 --20 0 40 80

40200 80 120

20 60

--20 0 40 8020 60

60 100

100

Ambient temperature, Ta -- °C

I

CC

2 -- Ta

IC current drain in operation, I

CC

2 -- mA

1.9

2.3

--40 100

Ambient temperature, Ta -- °C

Vref -- Ta

V

IN

= 12V

EN = 0V

V

IN

= 12V

EN = 5V

FB = 1V

No.A1761-6/9

Reference voltage, Vref -- mV

780

785

790

795

800

805

810

815

10

15

5

20

25

30

35

40

45

820

--40 --20 140

Ambient temperature, Ta -- °C

Iref -- Ta

FB pin bias current, Iref -- nA

0

50

--40 100

Ambient temperature, Ta -- °C

F

OSC

-- Ta

OSC

290

310

330

350

370

390

410

430

18

12

6

6.0

6.5

5.0

5.5

4.0

4.5

450

80

85

90

95

--40 100

Ambient temperature, Ta -- °C

D max -- Ta

Maximum ON DUTY, D max -- %

--40 100

Ambient temperature, Ta -- °C

F

OSCS

-- Ta

short-circuit protection, F

OSCS

-- kHz

0

24

3.0

3.5

7.0

--40 100

Ambient temperature, Ta -- °C

I

SS

-- Ta

Soft start current, I

SS

-- μA

--40 100

Ambient temperature, Ta -- °C

CC

Oscillation frequency, F -- kHzOscillation frequency during IC current drain at standby, I 1 -- μA

V

IN

= 12V

V

IN

= 12V

FB = 0.8V

V

IN

= 12V

V

IN

= 12V

V

IN

= 12V

SS = 0V

V

IN

= 12V

LV5813TT-TE-L-H

LV5813TT-TE-L-H

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