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MC74LVXT4052DTG

P1-P3P4-P6P7-P9P10-P12P13-P14
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 7
1 Publication Order Number:
MC74LVXT4052/D
MC74LVXT4052
Analog Multiplexer/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVXT4052 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from V
CC
to V
EE
).
The LVXT4052 is similar in pinout to the high−speed HC4052A
and the metal−gate MC14052B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
TTL levels.
This device has been designed so the ON resistance (R
ON
) is more
linear over input voltage than the R
ON
of metal−gate CMOS analog
switches and High−Speed CMOS analog switches.
Features
• Select Pins Compatible with TTL Levels
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Analog Power Supply Range (V
CC
− V
EE
) = −3.0 V to )3.0 V
• Digital (Control) Power Supply Range (V
CC
− GND) = 2.5 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal−Gate,
HSL, or VHC Counterparts
• Low Noise
• Designed to Operate on a Single Supply with V
EE
= GND,
or Using Split Supplies up to ±3.0 V
• Break−Before−Make Circuitry
• These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
TSSOP−16
DT SUFFIX
CASE 948F
SOIC−16
D SUFFIX
CASE 751B
LVXT4052G
AWLYWW
1
16
1
16
LVXT4052 = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
LVXT
4052
ALYWG
G
TSSOP−16
SOIC−16
1516 14 13 12 11 10
21 34567
V
CC
9
8
X2 X1 X X0 X3 A B
Y0 Y2 Y Y3 Y1 Enable V
EE
GND
PIN ASSIGNMENT
MC74LVXT4052
www.onsemi.com
2
Figure 1. Logic Diagram
Double−Pole, 4−Position Plus Common Off
FUNCTION TABLE
L
L
H
H
X
L
H
L
H
X
Control Inputs
ON Channels
Enable
Select
BA
X0
X1
X2
X3
L
L
L
L
H
X = Don’t Care
Y0
Y1
Y2
Y3
NONE
X0
12
X1
14
X2
15
X3
11
Y0
1
Y1
5
Y2
2
Y3
4
A
10
B
9
ENABLE
6
X SWITCH
Y SWITCH
X
13
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
Y
3
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch.
ORDERING INFORMATION
Device Package Shipping
†
MC74LVXT4052DG SOIC−16
(Pb−Free)
48 Units / Rail
MC74LVXT4052DR2G SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74LVXT4052DTG TSSOP−16
(Pb−Free)
96 Units / Rail
MC74LVXT4052DTRG TSSOP−16
(Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC74LVXT4052
www.onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
EE
Negative DC Supply Voltage (Referenced to GND) −7.0 to +0.5 V
V
CC
Positive DC Supply Voltage (Referenced to GND)
(Referenced to V
EE
)
−0.5 to +7.0
−0.5 to +7.0
V
V
IS
Analog Input Voltage V
EE
− 0.5 to V
CC
+ 0.5 V
V
IN
Digital Input Voltage (Referenced to GND) −0.5 to 7.0 V
I DC Current, Into or Out of Any Pin ±20 mA
T
STG
Storage Temperature Range −65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature under Bias +150
_C
JA
Thermal Resistance SOIC
TSSOP
143
164
°C/W
P
D
Power Dissipation in Still Air, SOIC
TSSOP
500
450
mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94−V0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
u2000
u200
u1000
V
I
LATCHUP
Latchup Performance Above V
CC
and Below GND at 125°C (Note 4) ±300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
EE
Negative DC Supply Voltage (Referenced to GND) −6.0 GND V
V
CC
Positive DC Supply Voltage (Referenced to GND)
(Referenced to V
EE
)
2.5
2.5
6.0
6.0
V
V
IS
Analog Input Voltage V
EE
V
CC
V
V
IN
Digital Input Voltage (Note 5) (Referenced to GND) 0 6.0 V
T
A
Operating Temperature Range, All Package Types −55 125
_C
t
r
, t
f
Input Rise/Fall Time V
CC
= 3.0 V ± 0.3 V
(Channel Select or Enable Inputs) V
CC
= 5.0 V ± 0.5 V
0
0
100
20
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100
1000
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 2. Failure Rate vs. Time Junction Temperature
NORMALIZED FAILURE RATE
TIME, YEARS
T
J
= 130_C
T
J
= 120_C
T
J
= 110_C
T
J
= 100_C
T
J
= 90_C
T
J
= 80_C
P1-P3P4-P6P7-P9P10-P12P13-P14

MC74LVXT4052DTG

Mfr. #:
Buy MC74LVXT4052DTG
Manufacturer:
ON Semiconductor
Description:
Multiplexer Switch ICs 2.5-6V Analog Mux/DeMux
Lifecycle:
New from this manufacturer.
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