IRF3808S/LPbF
7
www.irf.com © 2013 International Rectifier Submit Datasheet Feedback November 01, 2013
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) = DT/ Z
thJC
I
av
=
2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
25 50 75 100 125 150 175
Starting T
J
, Junction Temperature (°C)
0
100
200
300
400
500
E
A
R
,
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
TOP Single Pulse
BOTTOM 10% Duty Cycle
I
D
= 140A
1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
1000
10000
A
v
a
l
a
n
c
h
e
C
u
r
r
e
n
t
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Δ
Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
IRF3808S/LPbF
8
www.irf.com © 2013 International Rectifier Submit Datasheet Feedback November 01, 2013
Peak Diode Recovery dv/dt Test Circuit
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
+
-
+
+
+
-
-
-
R
G
V
DD
dv/dt controlled by R
G
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
*
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
* Reverse Polarity of D.U.T for P-Channel
V
GS
[ ]
[ ]
*** V
GS
= 5.0V for Logic Level and 3V Drive Devices
[ ] ***
Fig 17. For N-channel HEXFET
®
power MOSFETs
IRF3808S/LPbF
9
www.irf.com © 2013 International Rectifier Submit Datasheet Feedback November 01, 2013
D
2
Pak (TO-263AB) Part Marking Information
D
2
Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
DAT E CODE
YE AR 0 = 2000
WEEK 02
A = AS S E MB L Y S IT E CODE
RECT IF IER
INT ERNATIONAL
PART NUMBER
P = DE S I GNAT E S L E AD - F RE E
PRODUCT (OPTIONAL)
F530S
IN THE ASS EMBLY LINE "L"
AS SEMBLED ON WW 02, 2000
T HIS IS AN IRF530S WITH
LOT CODE 8024
INT ERNAT IONAL
LOGO
RECT IF IER
LOT CODE
ASSEMBLY
YEAR 0 = 2000
PART NUMBER
DAT E CODE
LINE L
WE E K 02
OR
F530S
LOGO
ASSEMBLY
LOT CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

IRF3808SPBF

Mfr. #:
Manufacturer:
Infineon / IR
Description:
MOSFET 75V 1 N-CH HEXFET 7mOhms 150nC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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