Datasheet
8/10
BD47xx series
TSZ02201-0R7R0G300020-1-2
© 2012 ROHM Co., Ltd. All rights reserved.
18.Nov.2012 Rev.005
www.rohm.com
TSZ22111・15・001
●Application Information
Explanation of Operation
BD47xx series has threshold voltages namely the detection voltage and release voltage. As the voltages applied to the
input reach their respective thresholds, the output switches from “High” to “Low” and from “Low” to “High”. The release
voltage has a hysteresis that is the value of the detection voltage +50mV (Typ.), preventing chattering in the output. When
the input is greater than the release voltage, the output is in a “High” state. When the input decreases from that state, the
output switches to “Low” upon reaching the detection voltage. When the input is less than the detection voltage, the output
is in a “Low” state. When the input increases from that state, the output switches to “High” upon reaching the release
voltage. Additionally, at least 0.85V input voltage is required for the circuit to function as expected. When the input falls
below the operating limit voltage, the output becomes unstable.
1
When the power supply is turned on, the output is still unstable until it reaches the operating limit voltage (V
OPL
) with a
given time t
PHL
. Therefore it is possible that the reset signal is not outputted when the rise time of V
DD
is faster than t
PHL
.
2
When V
DD
is greater than V
OPL
but less than the reset release voltage (VDET+VDET), the output voltages will switch to
Low.
3
If V
DD
exceeds the reset release voltage (VDET+VDET) then V
OUT
switches from L to H.
4
If V
DD
drops below the detection voltage (VDET) when the power supply is powered down or when there is a power
supply fluctuation, V
OUT
switches to L (with a delay of t
PHL
).
5
The potential difference between the detection voltage and the release voltage is known as the Hysteresis Width
(V
DET). The system is designed such that, the output does not toggle with power supply fluctuations within this hysteresis
width, malfunctions due to noise are prevented.
<Precautions>
Please be aware that when there is resistance on the power supply line, the detection voltage varies with voltage drops
caused by the IC current consumption.
Please connect a capacitor between V
DD
and GND when the power supply line has high impedance.
Fig.11 Timing Waveform
VDD
VDET+ΔVDET
VDET
VOPL
0V
tPHL
① ②
V
OUT
tPLH
tPHL
tPLH
③ ④
VOL
VOH
VDD
⑤
