C8051F310DK-K Datasheet C8051F310DK, C8051F310DK-A, C8051F310DK-B | P7-P9

C8051F31x

Rev. 0.7 7

4.1. System Clock Sources

The

C8051F310

device installed on the target board features a calibrated programmable internal oscillator which is

enabled as the system clock source on reset. After reset, the internal oscillator operates at a frequency of

3.0625 MHz (±2%) by default but may be configured by software to operate at other frequencies. Therefore, in many

applications an external oscillator is not required. However, if you wish to operate the C8051F310 device at a fre-

quency not available with the internal oscillator, an external crystal may be used. Refer to the

C8051F31x

data sheet

for more information on configuring the system clock source.

The target board is designed to facilitate the installation of an external crystal. Remove shorting blocks at headers

J9 and J10 and install the crystal at the pads marked Y1. Install a 10 M resistor at R9 and install capacitors at

C14 and C15 using values appropriate for the crystal you select. Refer to the C8051F31x data sheet for more infor-

mation on the use of external oscillators.

4.2. Switches and LEDs

Two switches are provided on the target board. Switch SW1 is connected to the RESET pin of the C8051F310.

Pressing SW1 puts the device into its hardware-reset state. Switch SW2 is connected to the C8051F310’s general

purpose I/O (GPIO) pin through headers. Pressing SW2 generates a logic low signal on the port pin. Remove the

shorting block from the header to disconnect SW2 from the port pins. The port pin signal is also routed to a pin on

the J1 I/O connector. See Table 1 for the port pins and headers corresponding to each switch.

Two LEDs are also provided on the target board. The red LED labeled PWR is used to indicate a power connection

to the target board. The green LED labeled with a port pin name is connected to the C8051F310’s GPIO pin

through headers. Remove the shorting block from the header to disconnect the LED from the port pin. The port pin

signal is also routed to a pin on the J1 I/O connector. See Table 1 for the port pins and headers corresponding to

each LED.

Table 1. Target Board I/O Descriptions

Description I/O Header

SW1 Reset none

SW2 P0.7 J3[3-4]

Green LED P3.3 J3[1-2]

Red LED PWR none

C8051F31x

8 Rev. 0.7

4.3. Expansion I/O Connector (J1)

The

-pin Expansion I/O connector J1 provides access to all signal pins of the C8051F

0 device. Pins for +3 V,

digital ground and the output of an on-board low-pass filter are also available. A small through-hole prototyping area

is also provided. All I/O signals routed to connector J1 are also routed to through-hole connection points between J1

and the prototyping area (see

Figure 4 on page 6

). Each connection point is labeled indicating the signal available at

the connection point. See Table 2 for a list of pin descriptions for J1.

4.4. Target Board DEBUG Interface (J4)

The

DEBUG

connector (J4) provides access to the

DEBUG

(C2) pins of the C8051F310. It is used to connect the

Serial Adapter or the USB Debug Adapter to the target board for in-circuit debugging and Flash programming.

Table 3 shows the

DEBUG

pin definitions.

Table 2. J1 Pin Descriptions

Pin # Description Pin # Description Pin # Description

1 +3VD (+3.3VDC) 13 P1.2 25 P2.6

2 PWM Output 14 P1.3 26 P2.7

3 P0.0 15 P1.4 27 P3.0

4 P0.1 16 P1.5 28 P3.1

5 P0.2 17 P1.6 29 P3.2

6 P0.3 18 P1.7 30 P3.3

7 P0.4 19 P2.0 31 P3.4

8 P0.5 20 P2.1 32 /RST (Reset)

9 P0.6 21 P2.2 33 GND (Ground)

10 P0.7 22 P2.3 34 GND (Ground)

11 P1.0 23 P2.4

12 P1.1 24 P2.5

Table 3. DEBUG Connector Pin Descriptions

Pin # Description

1 +3VD (+3.3VDC)

2, 3, 9 GND (Ground)

4C2D

5/RST (Reset)

6P3.0

7C2CK

8 Not Connected

10 USB Power

C8051F31x

Rev. 0.7 9

4.5. Serial Interface (J5)

A RS232 transceiver circuit and DB-9 (J5) connector are provided on the target board to facilitate serial connec-

tions to UART0 of the C8051F310. The TX, RX, RTS and CTS signals of UART0 may be connected to the DB-9

connector and transceiver by installing shorting blocks on header J3.

J3[5–6]- Install shorting block to connect UART0 TX (P0.4) to transceiver.

J3[7–8]- Install shorting block to connect UART0 RX (P0.5) to transceiver.

J3[9–10]- Install shorting block to connect UART0 RTS (P3.1) to transceiver.

J3[11–12]- Install shorting block to connect UART0 CTS (P3.2) to transceiver.

4.6. Analog I/O (J6)

Several of the C8051F310 target device’s port pins are connected to the J6 terminal block. Refer to Table 4 for the

J6 terminal block connections. Install a shorting block on J7[2-3] to connect the AIN2.4 input to the P2.4 pin of the

target device.

4.7. USB Debug Adapter Target Board Power Connector (J8)

The USB Debug Adapter includes a connection to provide power to the target board. This connection is routed

from J4[10] to J8[1]. Place a shorting block at header J8[2–3] to power the board directly from an ac/dc power

adapter. Place a shorting block at header J8[1–2] to power the board from the USB Debug Adapter. Please note

that the second option is not supported with either the EC1 or EC2 Serial Adapters.

4.8. Low-Pass Filter (J7)

The C8051F310 target board features a low-pass filter that may be connected to port pin P2.4. Install a shorting

block on J7[1–2] to connect the P2.4 pin of the target device to the low-pass filter input. The output of the low-pass

filter is routed to the PWM signal at J1[2]. The C8051F310 may be programmed to generate a PWM (Pulse-Width

Modulated) waveform which is then input to the low-pass filter to implement a user-controlled PWM digital-to-ana-

log converter. Refer to Applications Note “AN107: Implementing 16-Bit PWM Using the PCA” in the “documenta-

tion” directory on the CD-ROM for a discussion on generating a programmable dc voltage level with a PWM

waveform and low-pass filter.

Table 4. J6 Terminal Block Pin Descriptions

Pin # Description

1 P2.5 / AIN2.5

2AIN2.4

3 GND (Ground)

4 P0.0 / Vref (Voltage Reference)

P1-P3 P4-P6 P7-P9 P10-P12

C8051F310DK-K

Mfr. #:

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C8051F31X EVAL BRD

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