2008-2016 Microchip Technology Inc. DS20002124G-page 9
24AA02E48/24AA025E48/24AA02E64/24AA025E64
6.0 WRITE OPERATION
6.1 Byte Write
Following the Start condition from the master, the
device code (four bits), the chip address (three bits)
and the R/W bit which is a logic-low, is placed onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow once it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the word address and will be written into the Address
Pointer of the 24AA02XEXX. After receiving another
Acknowledge signal from the 24AA02XEXX, the
master device will transmit the data word to be written
into the addressed memory location. The
24AA02XEXX acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and, during this time, the 24AA02XEXX will
not generate Acknowledge signals (Figure 6-1).
6.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA02XEXX in the same
way as in a byte write. However, instead of generating
a Stop condition, the master transmits up to eight data
bytes to the 24AA02XEXX, which are temporarily
stored in the on-chip page buffer and will be written into
memory once the master has transmitted a Stop
condition. Upon receipt of each word, the three
lower-order Address Pointer bits (four for the
24AA025E48/24AA025E64) are internally incremented
by one.
The higher-order five bits (four for the
24AA025E48/24AA025E64) of the word address
remain constant. If the master should transmit more
than eight words (16 for the
24AA025E48/24AA025E64) prior to generating the
Stop condition, the address counter will roll over and the
previously received data will be overwritten. As with the
byte write operation, once the Stop condition is received
an internal write cycle will begin (Figure 6-2).
6.3 Write Protection
The upper half of the array (80h-FFh) is permanently
write-protected. Write operations to this address range
are inhibited. Read operations are not affected.
The remaining half of the array (00h-7Fh) can be
written to and read from normally.
FIGURE 6-1: BYTE WRITE
Note: Page write operations are limited to
writing bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address
Data
A
C
K
A
C
K
A
C
K
101
0
A2*A1*A0*
0
Chip
Select
Bits
Note: * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
