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9FGV1001B001NBGI

P1-P3P4-P6P7-P9P10-P12P13-P15
10©2018 Integrated Device Technology, Inc. July 5, 2018
9FGV1001 Datasheet
1
Single CMOS driver active for each output pair.
2
See Test Loads for details.
3
I
DDCORE
= I
DDA
+ I
DDDIG.
Table 13. Current Consumption
V
DDO
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, T
A
= -40°C to +85°C unless stated otherwise.
Parameter Symbol Conditions Minimum Typical Maximum Units Notes
V
DDREF
Supply Current I
DDREF
25MHz REFCLK. 4 7 mA
Core Supply Current I
DDCORE
2500MHz VCO, 25MHz REFCLK. 23 31 mA 3
Output Buffer Supply Current
(V
DDO2
)
I
DDOx
LVDS, 325MHz. 20 26 mA 2
LP-HCSL, 100MHz. 18 24 mA 2
LVCMOS, 50MHz. 15 20 mA 1,2
LVCMOS, 200MHz. 24 39 mA 1,2
Output Buffer Supply Current
(V
DDO0,
V
DDO1,
V
DDO3
–per
output)
I
DDOx
LVDS, 325MHz. 7 11 mA 2
LP-HCSL, 100MHz. 6 10 mA 2
LVCMOS, 50MHz. 4 7 mA 1,2
LVCMOS, 200MHz. 13 25 mA 1,2
Total Power Down Current I
DDPD
Programmable outputs in HCSL
mode, B37[6,0] = 0.
913mA2
Programmable outputs in LVDS
mode, B37[6,0] = 0.
24 31 mA 2
Programmable outputs in
LVCMOS1 mode, B37[6,0] = 0.
47mA2
11©2018 Integrated Device Technology, Inc. July 5, 2018
9FGV1001 Datasheet
I
2
C Bus Characteristics
Note: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
Table 14. I
2
C Bus DC Characteristics
Parameter Symbol Conditions Minimum Typical Maximum Units
Input High Level V
IH
— 0.7 x V
DDD
V
Input Low Level V
IL
— 0.3 x V
DDD
V
Hysteresis of Inputs V
HYS
—0.05 x V
DDD
V
Input Leakage Current I
IN
—-1 30μA
Output Low Voltage V
OL
I
OL
= 3mA. 0.4 V
Table 15. I
2
C Bus AC Characteristics
Parameter Symbol Conditions Minimum Typical Maximum Units
Serial Clock Frequency (SCL) F
SCLK
— 10 400 kHz
Bus free time between STOP and START t
BUF
—1.3 μs
Setup Time, START t
SU:START
—0.6 μs
Hold Time, START t
HD:START
—0.6 μs
Setup Time, Data Input (SDA) t
SU:DATA
—0.1 μs
Hold Time, Data Input (SDA) t
HD:DATA
—0 μs
Output Data Valid from Clock t
OVD
—0.9μs
Capacitive Load for Each Bus Line C
B
— 400 pF
Rise Time, Data and Clock (SDA, SCL) t
R
— 20 + 0.1 x C
B
300 ns
Fall Time, Data and Clock (SDA, SCL) t
F
— 20 + 0.1 x C
B
300 ns
High Time, Clock (SCL) t
HIGH
—0.6 μs
Low Time, Clock (SCL) t
LOW
—1.3 μs
Setup Time, STOP t
SU:STOP
—0.6 μs
12©2018 Integrated Device Technology, Inc. July 5, 2018
9FGV1001 Datasheet
Crystal Characteristics
Table 16. Recommended Crystal Characteristics
Parameter Value Units
Frequency
8–50 MHz
Resonance Mode
Fundamental –
Frequency Tolerance at 25°C
±20 ppm maximum
Frequency Stability, REF at 25°C Over Operating Temperature Range
±20 ppm maximum
Temperature Range (commercial)
0–70 °C
Temperature Range (industrial)
-40–85 °C
Equivalent Series Resistance (ESR)
50 Ω maximum
Shunt Capacitance (C
O
)
7 pF maximum
Load Capacitance (C
L
)
8 pF maximum
Drive Level
0.1 mW maximum
Aging per year
±5 ppm maximum
P1-P3P4-P6P7-P9P10-P12P13-P15

9FGV1001B001NBGI

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Clock Generators & Support Products 4 O/P 1INT PHI CLOCK
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