REV. C
ADF4217L/ADF4218L/ADF4219L
–9–
CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches; SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
POWER-DOWN
CONTROL
REF
IN
NC
NC
NO
SW3
SW2
SW1
50k⍀
BUFFER
TO R
COUNTER
NC = NORMALLY CLOSED
NO = NORMALLY OPEN
Figure 2. Reference Input Stage
IF/RF Input Stage
The IF/RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
500⍀500⍀
1.6V
BIAS
GENERATOR
RF
IN
A
RF
IN
B
AV
DD
AGND
Figure 3. IF/RF Input Stage
Prescaler
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the IF/RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. It is
based on a synchronous 4/5 core.
The prescaler is selectable. On the IF side, it can be set to either 8/9
(DB20 of the IF AB Counter Latch set to 0) or 16/17 (DB20 set
to 1). On the RF side of the ADF4217L/ADF4218L, it can be set
to 64/65 or 32/33. On the ADF4219L, the RF prescaler can be
set to 16/17 or 32/33. See Tables V, VI, VIII, and IX.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The devices are guaranteed to work when the
prescaler output is 188 MHz or less. Typically they will work
with 250 MHz output from the prescaler.
TO PFD
N = BP + A
LOAD
LOAD
MODULUS
CONTROL
FROM IF/RF
INPUT STAGE
11(13)-BIT
B COUNTER
6(5)-BIT
A COUNTER
PRESCALER
P/P+1
Figure 4. Reference Input Stage, A and B Counters
V
CP
– V
6
0
–6
0 5.00.5
I
CP
– mA
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
4
2
–2
–4
V
P
= 5V
I
CP
= 4mA
TPC 13. Charge Pump Output Characteristics
