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A1180LUA

P1-P3P4-P6P7-P9P10-P12P13-P15
Sensitive Two-Wire Field-Programmable
Chopper-Stabilized Unipolar Hall Effect Switches
A1180, A1181,
A1182, and A1183
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Power Derating
The device must be operated below the maximum junction
temperature of the device, T
J(max)
. Under certain combinations of
peak conditions, reliable operation may require derating sup-
plied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating T
J
. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, R
JA
, is a fi gure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, R
JC
, is
relatively small component of R
JA
. Ambient air temperature,
T
A
, and air motion are signifi cant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, P
D
), can
be estimated. The following formulas represent the fundamental
relationships used to estimate T
J
, at P
D
.
P
D
= V
IN
×
I
IN
(1)
T = P
D
×
R
JA
(2)
T
J
= T
A
+ ΔT (3)
For example, given common conditions such as: T
A
= 25°C,
V
CC
= 12 V, I
CC
= 4 mA, and R
JA
= 140 °C/W, then:
P
D
= V
CC
×
I
CC
= 12 V
×
4 mA = 48 mW
T = P
D
×
R
JA
= 48 mW
×
140 °C/W = 7°C
T
J
= T
A
+ T = 25°C + 7°C = 32°C
A worst-case estimate, P
D(max)
, represents the maximum allow-
able power level (V
CC(max)
, I
CC(max)
), without exceeding T
J(max)
,
at a selected R
JA
and T
A
.
Example: Reliability for V
CC
at T
A
=
150°C, package UA, using
minimum-K PCB.
Observe the worst-case ratings for the device, specifi cally:
R
JA
=
165°C/W, T
J(max)
=
165°C, V
CC(max)
=
24 V, and
I
CC(max)
=
17
mA.
Calculate the maximum allowable power level, P
D(max)
. First,
invert equation 3:
T
max
= T
J(max)
– T
A
= 165
°C
–
150
°C = 15
°C
This provides the allowable increase to T
J
resulting from internal
power dissipation. Then, invert equation 2:
P
D(max)
= T
max
÷ R
JA
= 15°C ÷ 165 °C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
V
CC(est)
= P
D(max)
÷ I
CC(max)
= 91 mW ÷ 17 mA = 5 V
The result indicates that, at T
A
, the application and device can
dissipate adequate amounts of heat at voltages ≤V
CC(est)
.
Compare V
CC(est)
to V
CC(max)
. If V
CC(est)
≤ V
CC(max)
, then reli-
able operation between V
CC(est)
and V
CC(max)
requires enhanced
R
JA
. If V
CC(est)
≥ V
CC(max)
, then operation between V
CC(est)
and
V
CC(max)
is reliable under these conditions.
Sensitive Two-Wire Field-Programmable
Chopper-Stabilized Unipolar Hall Effect Switches
A1180, A1181,
A1182, and A1183
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
PROGRAMMING PROTOCOL CHARACTERISTICS, over operating temperature range, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Programming Voltage
1
V
PL
Minimum voltage range during programming 4.5 5.0 5.5 V
V
PM
11.5 12.5 13.5 V
V
PH
25.0 26.0 27.0 V
Programming Current
2
I
PP
t
r
= 11 s; 5 V 26 V; C
BYP
= 0.1 F - 190 - mA
Pulse Width
t
d(0)
OFF time between programming bits 20 - - s
t
d(1)
Pulse duration for enable and addressing
sequences
20 - - s
t
d(P)
Pulse duration for fuse blowing 100 300 - s
Pulse Rise Time t
r
V
PL
to V
PM
;
V
PL
to V
PH
5-20s
Pulse Fall Time t
f
V
PM
to V
PL
; V
PH
to V
PL
5 - 100 s
1
Programming voltages are measured at the VCC pin.
2
A bypass capacitor with a minimum capacitance of 0.1 F must be connected from VCC to the GND pin of the A118x device in order to
provide the current necessary to blow the fuse.
V
PH
V+
t
V
PM
V
PL
0
T
d(1)
T
d(0)
T
d(P)
Figure 4. Pulse amplitudes and durations
Additional information on device programming and program-
ming products is available on www. allegromicro.com. Program-
ming hardware is available for purchase, and programming
software is available free of charge.
Programming Protocol
The operate switchpoint, B
OP
, can be fi eld-programmed. To do
so, a coded series of voltage pulses through the VCC pin is used
to set bitfi elds in onboard registers. The effect on the device
output can be monitored, and the registers can be cleared and
set repeatedly until the required B
OP
is achieved. To make the
setting permanent, bitfi eld-level solid state fuses are blown, and
fi nally, a device-level fuse is blown, blocking any further cod-
ing. It is not necessary to program the release switchpoint, B
RP
,
because the difference between B
OP
and B
RP
, referred to as the
hysteresis, B
HYS
, is fi xed.
The range of values between B
OP(min)
and B
OP(max)
is scaled to
31 increments. The actual change in magnetic fl ux (G) repre-
sented by each increment is indicated by B
RES
(see the Operating
Characteristics table; however, testing is the only method for
verifying the resulting B
OP
). For programming, the 31 incre-
ments are individually identifi ed using 5 data bits, which are
physically represented by 5 bitfi elds in the onboard registers.
By setting these bitfi elds, the corresponding calibration value is
programmed into the device.
Three voltage levels are used in programming the device: a low
voltage, V
PL
, a minimum required to sustain register settings; a
mid-level voltage, V
PM
, used to increment the address counter
in the device; and a high voltage, V
PH
, used to separate sets of
V
PM
pulses (when short in duration) and to blow fuses (when
long in duration). A fourth voltage level, essentially 0 V, is used
to clear the registers between pulse sequences. The pulse values
are shown in the Programming Protocol Characteristics table and
in fi gure 4.
Code Programming. Each bitfi eld must be individually set. To
do so, a pulse sequence must be transmitted for each bitfi eld that
is being set to 1. If more than one bitfi eld is being set to 1, all
pulse sequences must be sent, one after the other, without allow-
ing V
CC
to fall to zero (which clears the registers).
The same pulse sequence is used to provisionally set bitfi elds as
is used to permanently set bitfi eld-level fuses. The only differ-
ence is that when provisionally setting bitfi elds, no fuse-blowing
pulse is sent at the end of the pulse sequence.
Sensitive Two-Wire Field-Programmable
Chopper-Stabilized Unipolar Hall Effect Switches
A1180, A1181,
A1182, and A1183
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The pulse sequences consist of the following groups of pulses:
1. An enable sequence.
2. A bitfi eld address sequence.
3. When permanently setting the bitfi eld, a long V
PH
fuse-blow-
ing pulse. (Note: Blown bit fuses cannot be reset.)
4. When permanently setting the bitfi eld, the level of V
CC
must
be allowed to drop to zero between each pulse sequence, in
order to clear all registers. However, when provisionally set-
ting bitfi elds, V
CC
must be maintained at V
PL
between pulse
sequences, in order to maintain the prior bitfi eld settings while
preparing to set additional bitfi elds.
Bitfi elds that are not set are evaluated as zeros. The bitfi eld-level
fuses for 0 value bitfi elds are never blown. This prevents inad-
vertently setting the bitfi eld to 1. Instead, blowing the device-
level fuse protects the 0 bitfi elds from being accidentally set in
the future.
When provisionally trying the calibration value, one pulse
sequence is used, using decimal values. The sequence for setting
the value 5
10
is shown in fi gure 5.
When permanently setting values, the bitfi elds must be set indi-
vidually, and 5
10
must be programmed as binary 101. Bit 3 is
set to 1 (000100
2
, which is 4
10
), then bit 1 is set to 1 (000001
2
,
which is 1
10
). Bit 2 is ignored, and so remains 0.Two pulse
sequences for permanently setting the calibration value 5 are
shown in fi gure 6. The fi nal V
PH
pulse is maintained for a longer
period, enough to blow the corresponding bitfi eld-level fuse.
V
PH
V+
t
V
PM
V
PL
0
Encode 00100
2
(4
10
)
Enable
Address
Address
Blow BlowEnable
Encode 00001
2
(1
10
)
Figure 6. Pulse sequence to permanently encode calibration value 5 (101 binary, or
bitfi eld address 3 and bitfi eld address 1).
V
PH
V+
t
V
PM
V
PL
0
Try 5
10
Enable Address Clear
Optional
Monitoring
Figure 5. Pulse sequence to provisionally try calibration value 5.
P1-P3P4-P6P7-P9P10-P12P13-P15

A1180LUA

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