©2011 Silicon Storage Technology, Inc. DS25041A 05/11
5
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Microchip Technology Company
Figure 4: Pin Assignments for 48-Ball WFBGA
Table 1: Pin Description
Symbol Pin Name Functions
A
MS
1
-A
0
1. A
MS
= Most significant address
A
MS
=A
18
Address Inputs To provide memory addresses.
During Sector-Erase A
MS
-A
11
address lines will select the sector.
During Block-Erase A
MS
-A
15
address lines will select the block.
DQ
15
-DQ
0
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST# Reset To reset and return the device to Read mode.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
V
DD
Power Supply To provide power supply voltage: 2.7-3.6V
V
SS
Ground
NC No Connection Unconnected pins.
RY/BY# Ready/Busy# To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
T1.2 25041
A2
A1
A0
CE#
V
SS
A4
A3
A5
DQ8
OE#
DQ0
A6
A7
A18
DQ10
DQ9
DQ1
A17
WP#
NC
DQ2
NC
DQ3
NC
V
DD
WE#
DQ12
RST#
RY/BY#
NC
DQ13
A9
A10
A8
DQ4
DQ5
DQ14
A11
A13
A12
DQ11
DQ6
DQ15
A14
A15
A16
DQ7
V
SS
TOP VIEW (balls facing down)
AB C D E F G H J K L
6
5
4
3
2
1
1434 48-wfbga MAQ P3.0