ABRIDGED DATA SHEET
Note 1: Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 4: Typical value represents the internal parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 5: Guaranteed by design and/or characterization only. Not production tested.
Note 6: V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values
of V
TL
, V
TH
, and V
HY
.
Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8: The voltage on IO must be less than or equal to V
IL(MAX)
at all times the master is driving IO to a logic 0 level.
Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic 0.
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: Defines maximum possible bit rate. Equal to 1/(t
W0L(MIN)
+ t
REC(MIN)
).
Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 15: Interval after t
RSTL
during which a bus master can read a logic 0 on IO if there is a DS28E15 present. The power-up pres-
ence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 16:ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1L(MAX)
+ t
F
- ε and t
W0L(MAX)
+ t
F
- ε, respectively.
Note 17: d in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RL(MAX)
+ t
F
.
Note 18: Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO during
the programming interval and SHA-256 computation should be such that the voltage at IO is greater than or equal to 2.0V.
Note 19: Refer to the full data sheet.
Note 20: Refer to the full data sheet.
Note 21: Write-cycle endurance is tested in compliance with JESD47G.
Note 22: Not 100% production tested; guaranteed by reliability monitor sampling.
Electrical Characteristics (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
DS28E15 DeepCover Secure Authenticator with
1-Wire SHA-256 and 512-Bit User EEPROM
www.maximintegrated.com
Maxim Integrated
│
3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EEPROM
Programming Current I
PROG
V
PUP
= 3.63V (Notes 5, 18) 1 mA
Programming Time for a 32-Bit
Segment or Page Protection
t
PRD
Refer to the full data sheet.
ms
Programming Time for the Secret t
PRS
ms
Write/Erase Cycling Endurance N
CY
T
A
= +85NC (Notes 21, 22)
100k —
Data Retention t
DR
T
A
= +85NC (Notes 23, 24, 25)
10 Years
SHA-256 ENGINE
Computation Current I
CSHA
Refer to the full data sheet.
mA
Computation Time t
CSHA
ms
