AD9830
–8–
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
0
–10
–90
START 0Hz STOP 25MHz
–40
–60
–70
–80
–20
–30
–50
Figure 14. f
MCLK
= 50 MHz, f
OUT
= 9.1 MHz, Frequency
Word = 2E978D50
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
0
–10
–90
START 0Hz STOP 25MHz
–40
–60
–70
–80
–20
–30
–50
Figure 15. f
MCLK
= 50 MHz, f
OUT
= 11.1 MHz, Frequency
Word = 38D4FDF4
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
0
–10
–90
START 0Hz STOP 25MHz
–40
–60
–70
–80
–20
–30
–50
Figure 16. f
MCLK
= 50 MHz, f
OUT
= 13.1 MHz, Frequency
Word = 43126E98
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
0
–10
–90
START 0Hz STOP 25MHz
–40
–60
–70
–80
–20
–30
–50
Figure 11. f
MCLK
= 50 MHz, f
OUT
= 2.1 MHz, Frequency
Word = ACO8312
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
0
–10
–90
START 0Hz STOP 25MHz
–40
–60
–70
–80
–20
–30
–50
Figure 12. f
MCLK
= 50 MHz, f
OUT
= 3.1 MHz, Frequency
Word = FDF3B64
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
0
–10
–90
START 0Hz STOP 25MHz
–40
–60
–70
–80
–20
–30
–50
Figure 13. f
MCLK
= 50 MHz, f
OUT
= 7.1 MHz, Frequency
Word = 245A1CAC
REV. B
AD9830
–9–
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
0
–10
–90
START 0Hz STOP 25MHz
–40
–60
–70
–80
–20
–30
–50
Figure 17. f
MCLK
= 50 MHz, f
OUT
= 16.5 MHz, Frequency
Word = 547AE148
Register Size Description
FREQ0 REG 32 Bits Frequency Register 0. This defines
the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
FREQ1 REG 32 Bits Frequency Register 1. This de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
PHASE0 REG 12 Bits Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the out-
put of the phase accumulator.
PHASE1 REG 12 Bits Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the
contents of this register are added
to the output of the phase
accumulator.
PHASE2 REG 12 Bits Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the
contents of this register are added
to the output of the phase
accumulator.
PHASE3 REG 12 Bits Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the out-
put of the phase accumulator.
Figure 18. AD9830 Control Registers
A2 A1 A0 Destination Register
0 0 0 FREQ0 REG 16 LSBs
0 0 1 FREQ0 REG 16 MSBs
0 1 0 FREQ1 REG 16 LSBs
0 1 1 FREQ1 REG 16 MSBs
1 0 0 PHASE0 REG
1 0 1 PHASE1 REG
1 1 0 PHASE2 REG
1 1 1 PHASE3 REG
Figure 19. Addressing the Control Registers
D15 D0
MSB LSB
Figure 20. Frequency Register Bits
D15 D14 D13 D12 D11 D0
X XXXMSB LSB
X = Don't Care
Figure 21. Phase Register Bits
REV. B
AD9830
–10–
CIRCUIT DESCRIPTION
The AD9830 provides an exciting new level of integration
for the RF/Communications system designer. The AD9830
combines the Numerical Controlled Oscillator (NCO), SINE
Look-Up table, Frequency and Phase Modulators, and a
Digital-to-Analog Converter on a single integrated circuit.
The internal circuitry of the AD9830 consists of three main
sections. These are:
Numerical Controlled Oscillator (NCO) + Phase Modulator
SINE Look-Up Table
Digital-to-Analog Converter
The AD9830 is a fully integrated Direct Digital Synthesis
(DDS) chip. The chip requires one reference clock, two low
precision resistors and eight decoupling capacitors to provide
digitally created sine waves up to 25 MHz. In addition to the
generation of this RF signal, the chip is fully capable of a broad
range of simple and complex modulation schemes. These
modulation schemes are fully implemented in the digital do-
main allowing accurate and simple realization of complex
modulation algorithms using DSP techniques.
THEORY OF OPERATION
Sine waves are typically thought of in terms of their magnitude
form a (t) = sin (ωt). However, these are nonlinear and not
easy to generate except through piece wise construction. On
the other hand, the angular information is linear in nature.
That is, the phase angle rotates through a fixed angle for each
unit of time. The angular rate depends on the frequency of the
signal by the traditional rate of ω = 2πf
MAGNITUDE
PHASE
+1
0
–1
2
π
0
Figure 22. Sine Wave
Knowing that the phase of a sine wave is linear and given a ref-
erence interval (clock period), the phase rotation for that period
can be determined.
Phase = ωδt
Solving for ω
ω = Phase/δt = 2πf
Solving for f and substituting the reference clock frequency for
the reference period (1/f
MCLK
= δt)
f = Phase × f
MCLK
/2π
The AD9830 builds the output based on this simple equation.
A simple DDS chip can implement this equation with three
major subcircuits.
Numerical Controlled Oscillator + Phase Modulator
This consists of two frequency select registers, a phase accumu-
lator and four phase offset registers. The main component of
the NCO is a 32-bit phase accumulator which assembles the
phase component of the output signal. Continuous time signals
have a phase range of 0 to 2π. Outside this range of numbers,
the sinusoid functions repeat themselves in a periodic manner.
The digital implementation is no different. The accumulator
simply scales the range of phase numbers into a multibit digital
word. The phase accumulator in the AD9830 is implemented
with 32 bits. Therefore, in the AD9830, 2π = 2
32
. Likewise,
the Phase term is scaled into this range of numbers 0 < Phase
< 2
32
–1. Making these substitutions into the equation above
f = Phase × f
MCLK
/2
32
where 0 < Phase < 2
32
With a clock signal of 50 MHz and a phase word of 051EB852
hex
f = 51EB852 × 50 MHz/2
32
= 1.000000000931 MHz
The input to the phase accumulator (i.e., the phase step) can be
selected either from the FREQ0 Register or FREQ1 Register
and this is controlled by the FSELECT pin. NCOs inherently
generate continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies. More com-
plex frequency modulation schemes can be implemented by up-
dating the contents of these registers. This facilitates complex
frequency modulation schemes, such as GMSK.
Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit PHASE Registers. The con-
tents of this register are added to the most significant bits of the
NCO. The AD9830 has four PHASE registers. The resolution
of the phase registers equals 2π/4096.
Sine Look-Up Table (LUT)
To make the output useful, the signal must be converted from
phase information into a sinusoidal value. Since phase informa-
tion maps directly into amplitude, a ROM LUT converts the
phase information into amplitude. To do this, the digital phase
information is used to address a sine ROM LUT. Although the
NCO contains a 32-bit phase accumulator, the output of the
NCO is truncated to 12 bits. Using the full resolution of the
phase accumulator is impractical and unnecessary as this would
require a look-up table of 2
32
entries.
It is necessary only to have sufficient phase resolution in the
LUTs such that the dc error of the output waveform is domi-
nated by the quantization error in the DAC. This requires the
look-up table to have two more bits of phase resolution than the
10-bit DAC.
Digital-to-Analog Converter
The AD9830 includes a high impedance current source 10-bit
DAC, capable of driving a wide range of loads at different
speeds. Full-scale output current can be adjusted, for optimum
power and external load requirements, through the use of a
single external resistor (R
SET
).
The DAC can be configured for single or differential ended op-
eration.
IOUT can be tied directly to AGND for single ended
operation or through a load resistor to develop an output volt-
age. The load resistor can be any value required, as long as the
REV. B

AD9830ASTZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized Direct Digital Synthesizer
Lifecycle:
New from this manufacturer.
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