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ADG5412BRUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
Data Sheet ADG5412/ADG5413
Rev. C | Page 7 of 19
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
DIGITAL INPUTS
Input High Voltage, V
INH
2.0 V min
Input Low Voltage, V
INL
0.8 V max
Input Current, I
INL
or I
INH
0.002 µA typ V
IN
= V
GND
or V
DD
±0.1
µA max
Digital Input Capacitance, C
IN
2.5 pF typ
DYNAMIC CHARACTERISTICS
1
t
ON
180 ns typ R
L
= 300 Ω, C
L
= 35 pF
220 230 248 ns max V
S
= 18 V; see Figure 31
t
OFF
130 ns typ R
L
= 300 Ω, C
L
= 35 pF
169 167 174 ns max V
S
= 18 V; see Figure 31
Break-Before-Make Time Delay, t
D
(ADG5413 Only)
25 ns typ R
L
= 300 Ω, C
L
= 35 pF
8 ns min V
S1
= V
S2
= 18 V; see Figure 30
Charge Injection, Q
INJ
280 pC typ V
S
= 18 V, R
S
= 0 Ω, C
L
= 1 nF;
see Figure 32
Off Isolation −78 dB typ R
L
= 50 Ω, C
L
= 5 pF,
f = 100 kHz; see Figure 26
Channel-to-Channel Crosstalk
−70
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Figure 25
Total Harmonic Distortion + Noise 0.03 % typ R
L
= 1 kΩ, 18 V p-p, f = 20 Hz
to 20 kHz; see Figure 28
−3 dB Bandwidth 174 MHz typ R
L
= 50 Ω, C
L
= 5 pF; see
Figure 29
Insertion Loss −0.8 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 29
C
S
(Off ) 18 pF typ V
S
= 18 V, f = 1 MHz
C
D
(Off ) 18 pF typ V
S
= 18 V, f = 1 MHz
C
D
(On), C
S
(On) 58 pF typ V
S
= 18 V, f = 1 MHz
POWER REQUIREMENTS V
DD
= 39.6 V
I
DD
80 µA typ Digital inputs = 0 V or V
DD
100 130 µA max
V
DD
9/40 V min/V max GND = 0 V, V
SS
= 0 V
1
Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR Dx
V
DD
= +15 V, V
SS
= −15 V
TSSOP (θ
JA
= 112.6°C/W) 89 59 37 mA maximum
LFCSP (θ
JA
= 30.4°C/W) 160 94 49 mA maximum
V
DD
= +20 V, V
SS
= −20 V
TSSOP (θ
JA
= 112.6°C/W) 95 63 39 mA maximum
LFCSP (θ
JA
= 30.4°C/W) 170 98 50 mA maximum
V
DD
= 12 V, V
SS
= 0 V
TSSOP (θ
JA
= 112.6°C/W) 61 43 29 mA maximum
LFCSP (θ
JA
= 30.4°C/W) 110 70 42 mA maximum
V
DD
= 36 V, V
SS
= 0 V
TSSOP (θ
JA
= 112.6°C/W) 80 54 35 mA maximum
LFCSP (θ
JA
= 30.4°C/W)
144
87
47
mA maximum
ADG5412/ADG5413 Data Sheet
Rev. C | Page 8 of 19
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 6.
Parameter Rating
V
DD
to V
SS
48 V
V
DD
to GND −0.3 V to +48 V
V
SS
to GND +0.3 V to −48 V
Analog Inputs
1
V
SS
− 0.3 V to V
DD
+ 0.3 V or
30 mA, whichever occurs first
Digital Inputs
1
V
SS
− 0.3 V to V
DD
+ 0.3 V or
30 mA, whichever occurs first
Peak Current, Sx or Dx Pins
278 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current, Sx or Dx
2
Data + 15%
Temperature Range
Operating −40°C to +125°C
Storage −65°C to +150°C
Junction Temperature 150°C
Thermal Impedance, θ
JA
16-Lead TSSOP (4-Layer Board) 112.6°C/W
16-Lead LFCSP (4-Layer Board) 30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
1
Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2
See Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
Data Sheet ADG5412/ADG5413
Rev. C | Page 9 of 19
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
1
D1 2
S1 3
V
SS
4
IN2
16
D215
S214
V
DD
13
GND 5 NIC12
S4
6
S3
11
D4 7 D310
IN4 8 IN39
ADG5412/
ADG5413
TOP VIEW
(Not to Scale)
09202-002
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
LEAVE THIS PIN FLOATING.
Figure 2. TSSOP Pin Configuration
S1
V
SS
GND
S4
V
DD
S2
NIC
S3
D4
IN4
IN3
D3
IN1
D1
IN2
D2
09202-003
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
ADG5412/
ADG5413
TOP VIEW
NOTES
1. NIC = NOT INTERNALLY CONNECTED. LEAVE THIS PIN FLOATING.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL
CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED
TO THE SUBSTRATE, V
SS
.
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 15 IN1 Logic Control Input 1.
2 16 D1 Drain Terminal 1. This pin can be an input or output.
3 1 S1 Source Terminal 1. This pin can be an input or output.
4 2 V
SS
Most Negative Power Supply Potential.
5 3 GND Ground (0 V) Reference.
6 4 S4 Source Terminal 4. This pin can be an input or output.
7 5 D4 Drain Terminal 4. This pin can be an input or output.
8 6 IN4 Logic Control Input 4.
9 7 IN3 Logic Control Input 3.
10 8 D3 Drain Terminal 3. This pin can be an input or output.
11 9 S3 Source Terminal 3. This pin can be an input or output.
12 10 NIC Not Internally Connected. Leave this pin floating.
13 11 V
DD
Most Positive Power Supply Potential.
14 12 S2 Source Terminal 2. This pin can be an input or output.
15 13 D2 Drain Terminal 2. This pin can be an input or output.
16 14 IN2 Logic Control Input 2.
EP Exposed Pad
The exposed pad is connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the
substrate, V
SS
.
Table 8. ADG5412 Truth Table
INx Switch Condition
1 On
0 Off
Table 9. ADG5413 Truth Table
INx S1, S4 S2, S3
0 Off On
1 On Off
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

ADG5412BRUZ

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Buy ADG5412BRUZ
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs 9 Ohm -78dB 160MHz High VTG Latch-up
Lifecycle:
New from this manufacturer.
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