6
FN9250.2
March 21, 2008
On the ISL8702, enabling of on or off sequencing can also be
signaled via the SEQ_EN input pin once voltage compliance is
met. Initially the SEQ_EN pin should be held low and released
when sequence start is desired. The on sequence of the
ENABLE outputs is as previously described. The off sequence
feature is only available on the variants having the SEQ_EN or
the SEQ_EN# inputs, this being the ISL8702. The sequence is
D off, then C off, then B off and finally A off. Once SEQ_EN
(SEQ_EN#) is signaled low (high) the TIME cap is charged to
2V once again. Once this Vth is reached ENABLE_D
transitions to its reset state and CTIM is discharged. A delay
and subsequent sequence off is then determined by TD resistor
to ENABLE_C. Likewise, a delay to ENABLE_B and then
ENABLE_A turn-off is determined by TC and TB resistor values
respectively.
With the ISL8700, ISL8701, a quasi down sequencing of the
ENABLE outputs can be achieved by loading the ENABLE pins
with various value capacitors to ground. When a simultaneous
output latch off is invoked, the caps will set the falling ramp of
the various ENABLE outputs thus adjusting the time to Vth for
various DC/DC convertors or other circuitry.
Regardless of IC variant, the FAULT signal is always valid at
operational voltages and can be used as justification for
SEQ_EN release or even controlled with an RC timer for
sequence on.
Programming the Undervoltage and Overvoltage
Limits
When choosing resistors for the divider, remember to keep the
current through the string bounded by power loss at the top end
and noise immunity at the bottom end. For most applications,
total divider resistance in the 10kΩ to 1000kΩ range is
advisable with high precision resistors being used to reduce
monitoring error. Although for the ISL870x two dividers of two
resistors each can be employed to separately monitor the OV
and UV levels for the V
IN
voltage which will be discussed here
using a single three resistor string for monitoring the V
IN
voltage, referencing Figure 1. In the three resistor divider string
with R
u
(upper), R
m
(middle) and R
l
(lower), the ratios of each
in combination to the other two is balanced to achieve the
desired UV and OV trip levels. Although this IC has a bias
range of 2.5V to 24V (12V for ISL8702), it can monitor any
voltage >1.22V.
The ratio of the desired overvoltage trip point to the internal
reference is equal to the ratio of the two upper resistors to the
lowest (ground connected) resistor.
The ratio of the desired undervoltage trip point to the internal
reference voltage is equal to the ratio of the uppermost (voltage
connected) resistor to the lower two resistors.
These assumptions are true for both rising (turn-on) or falling
(shutdown) voltages.
The following is a practical example worked out. For detailed
equations on how to perform this operation for a given supply
requirement, please refer to the next section.
1. Determine if turn-on or shutdown limits are preferred and
in this example we will determine the resistor values
based on the shutdown limits.
2. Establish lower and upper trip level: 12V ±10% or 13.2V
(OV) and 10.8V (UV)
3. Establish total resistor string value: 100kΩ, I
r
= divider
current
4. (R
m
+ R
l
) x I
r
= 1.1V @ UV and R
l
x I
r
= 1.2V @ OV
5. R
m
+ R
l
= 1.1V/Ir @ UV = R
m
+ R
l
= 1.1V/(10.8V/100kΩ)
= 10.370kΩ
6. R
l
= 1.2V/Ir @ OV = Rl = 1.2V/(13.2V/100kΩ) = 9.242kΩ
7. R
m
= 10.370kΩ - 9.242kΩ = 1.128kΩ
8. R
u
= 100kΩ - 10.370kΩ = 89.630kΩ
9. Choose standard value resistors that most closely
approximate these ideal values. Choosing a different total
divider resistance value may yield a more ideal ratio with
available resistors values.
In our example with the closest standard values of
R
u
= 90.9kΩ, R
m
= 1.13kΩ and R
l
= 9.31kΩ, the nominal UV
falling and OV rising will be at 10.9V and 13.3V respectively.
An Advanced Tutorial on Setting UV and OV
Levels
This section discusses in additional detail the nuances of
setting the UV and OV levels, providing more insight into the
ISL870x than the earlier text.
The following equation set can alternatively be used to work
out ideal values for a 3 resistor divider string of R
u
, R
m
and
R
l
. These equations assume that V
REF
is the center point
between V
UVRvth
and V
UVFvth
(i.e. (V
UVRvth
+ V
UVFvth
)/2
= 1.17V), I
load
is the load current in the resistor string
(i.e. V
IN
/(R
u
+ R
m
+ R
l
)), V
IN
is the nominal input voltage
and V
tol
is the acceptable voltage tolerance, such that the
UV and OV thresholds are centered at V
IN
± V
tol
. The actual
acceptable voltage window will also be affected by the
hysteresis at the UV and OV pins. This hysteresis is
amplified by the resistor string such that the hysteresis at the
top of the string is calculated in Equation 1:
This means that the V
IN
± V
tol
thresholds will exhibit
hysteresis resulting in thresholds of V
IN
+ V
tol
± V
hys
/2 and
V
IN
- V
tol
± V
hys
/2.
There is a window between the V
IN
rising UV threshold and
the V
IN
falling OV threshold where the input level is
guaranteed not to be detected as a fault. This window exists
between the limits V
IN
± (V
tol
- V
hys
/2). There is an
extension of this window in each direction up to
V
IN
±(V
tol
+V
hys
/2), where the voltage may or may not be
Vhys V
UVhys
= V
OUT
V
REF
⁄×
(EQ. 1)
ISL8700, ISL8701, ISL8702
