11
FN9250.2
March 21, 2008
Application Concerns and Recommendations
When designing the ISL8700 family of products into
applications with low supply voltages such as 3.3V,
additional filtering to help reduce system noise on the
voltage supply input is necessary to ensure proper voltage
sequencing operation. It is important that the
user-programmed UV threshold is set sufficiently above (i.e.
>200mV) the ISL8700 IC’s internal POR level, V
IN_POR
,
over the entire operating temperature range. Best design
practices include proper decoupling on the supply input (i.e.
at least 1µF) as well as an RC filter that can adequately
suppress noise on the supply in the user’s application,
whereby the resistor should be kept < 13Ω to reduce voltage
loss to the already low biased VIN pin.
Coupling from the ENABLE_X pins to the sensitive UV and
OV pins can cause false OV/UV events to be detected. This
is most relevant for ISL8700, ISL8702 parts due to the
ENABLE_A and OV pins being adjacent. This coupling can
be reduced by adding a ground trace between UV and the
ENABLE/FAULT signals, as shown in Figure 14. The PCB
traces on OV and UV should be kept as small as practical
and the ENABLE_X and FAULT traces should ideally not be
routed under/over the OV/UV traces on different PCB layers
unless there is a ground or power plane in between. Other
methods that can be used to eliminate this issue are by
reducing the value of the resistors in the network connected
to UV and OV (R
2
, R
3
, R
5
in Figure 15) or by adding small
decoupling capacitors to OV and UV (C
2
and C
7
in
Figure 15). Both these methods act to reduce the AC
impedance at the nodes, although the latter method acts to
filter the signals, which will also cause an increase in the
time that a UV/OV fault takes to be detected
.
When the ISL870x is implemented on a hot swappable card
that is plugged into an always powered passive back plane,
an RC filter is required on the V
IN
pin to prevent a high dv/dt
transient. With the already existing 1µF decoupling capacitor,
the addition of a small series R (<13Ω) to provide a time
constant >50µs is all that is necessary.
Only the ISL8702 has a V
IN
limitation of 14V maximum.
FIGURE 14. LAYOUT DETAIL OF GND BETWEEN PINS 4 AND 5
PIN 4
PIN 5
GND
GND
ISL8700, ISL8701, ISL8702
