7
FN9250.2
March 21, 2008
detected as a fault, depending on the direction from which it
is approached. These two equations may be used to
determine the required value of Vtol for a given system. For
example, if V
IN
is 12V, Vhys = (0.1 x 12)/1.17 = 1.03V. If V
IN
must remain within 12V ± 1.5V, V
tol
= 1.5 - 1.03/2 = 0.99V.
This will give a window of 12 ±0.48V where the system is
guaranteed not to be in fault and a limit of 12 ±1.5V beyond
which the system is guaranteed to be in fault.
It is wise to check both these voltages for if the latter is made
too tight, the former will cease to exist. This point comes
when V
tol
< V
hys
/2 and results from the fact that the
acceptable window for the OV pin no longer aligns with the
acceptable window for the UV pin. In this case, the
application will have to be changed such that UV and OV are
provided separate resistor strings. In this case the UV and
OV thresholds can be individually controlled by adjusting the
relevant divider.
The previous example will give voltage thresholds:
with V
IN
rising
with V
IN
falling
So with a single three resistor string, the resistor values can
be calculated using Equation 4:
For the above example with Vtol = 0.99V, assuming a 100µA
Iload at V
IN
= 12V:
R
l
= 10.7kΩ
R
m
= 1.9kΩ
R
u
= 107.3kΩ
Programming the ENABLE Output Delays
The delay timing between the four sequenced ENABLE outputs
are programmed with four external passive components. The
delay from a valid V
IN
(ISL8700 and ISL8701) to ENABLE_A
and SEQ_EN being valid (ISL8702) to ENABLE_A is
determined by the value of the capacitor on the TIME pin to
GND. The external TIME pin capacitor is charged with a 2.6µA
current source. Once the voltage on TIME is charged up to the
internal reference voltage,
(V
TIME_VTH
) the ENABLE_A output
is released out of its reset state. The capacitor value for a
desired delay (±10%) to ENABLE_A once V
IN
and SEQ_EN
where applicable has been satisfied is determined by using
Equation 5:
Once ENABLE_A reaches
V
TIME_VTH
, the TIME pin is pulled
low in preparation for a sequenced off signal via SEQ_EN. At
this time, the sequencing of the subsequent outputs is started.
ENABLE_B is released out of reset after a programmable time,
then ENABLE_C, then ENABLE _D, all with their own
programmed delay times.
The subsequent delay times are programmed with a single
external resistor for each ENABLE output providing maximum
flexibility to the designer through the choice of the resistor value
connected from TB, TC and TD pins to GND. The resistor
values determine the charge and discharge rate of an internal
capacitor comprising an RC time constant for an oscillator
whose output is fed into a counter generating the timing delay
to ENABLE output sequencing.
The R
TX
value for a given delay time is defined as Equation 6:
Vr V
IN
V
tol
V
hys
2⁄+– 11.5Vand==
(EQ. 2)
Vr V
IN
V
tol
V
hys
2⁄++ 13.5V==
Vf V
IN
V
tol
V
hys
2⁄–+ 12.5Vand==
(EQ. 3)
Vf V
IN
V
tol
V
hys
2⁄–– 10.5V==
R
I
V
REF
I
load
⁄()1V
tol
– V
IN
⁄()=
(EQ. 4)
R
m
2V
REF
V
tol
×()V
IN
I
load
×()⁄=
R
u
1I
load
⁄()V
IN
V
REF
–()1V
tol
+ V
IN
⁄()×=
C
TIME
t
VINSEQpd
770kΩ⁄=
(EQ. 5)
R
TX
t
del
1667nF
---------------------
=
(EQ. 6)
ISL8700, ISL8701, ISL8702
