I²C bus interface LNBH23
14/32 Doc ID 13356 Rev 8
6 I²C bus interface
Data transmission from main MCU to the LNBH23 and vice versa takes place through the 2
wires I²C bus Interface, consisting of the 2 lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
6.1 Data validity
As shown in
Figure 5
, the data on the SDA line must be stable during the high semi-period
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.
6.2 Start and stop condition
As shown in
Figure 6
a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
6.3 Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
6.4 Acknowledge
The master (MCU) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see
Figure 7
). The peripheral (LNBH23) that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
this clock pulse. The peripheral which has been addressed has to generate acknowledge
after the reception of each byte, otherwise the SDA line remains at the HIGH level during the
ninth clock pulse time. In this case the master transmitter can generate the STOP
information in order to abort the transfer. The LNBH23 won't generate acknowledge if the
V
CC
supply is below the under voltage lockout threshold (6.7 V typ.).
6.5 Transmission without acknowledge
Avoiding to detect the acknowledges of the LNBH23, the MCU can use a simpler
transmission: simply it waits one clock cycle without checking the slave acknowledging, and
sends the new data. This approach of course is less protected from misworking and
decreases the noise immunity.
