LTC4257
16
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Load Capacitor
IEEE 802.3af requires that the PD maintain a minimum
load capacitance of 5µF. It is permissible to have a much
larger load capacitor and the LTC4257 can charge very
large load capacitors before thermal issues become a
problem. However, the load capacitor must not be too
large or the PD design may violate two IEEE 802.3af
requirements. The LTC4257 goes into current limit at
turn-on and charges the load capacitor with between
300mA and 400mA. The IEEE specification allows this
level of inrush current for up to 50ms. Therefore, it is
necessary that the PD complete charging of the capacitor
within the 50ms time limit. With a maximum input voltage
of –57V, these conditions limit the size of the load
capacitor to 250µF.
Very small output capacitors ( 10µF) will charge very
quickly in current limit. The rapidly changing voltage at
the output may reduce the current limit temporarily,
causing the capacitor to charge at a somewhat reduced
rate. Conversely, charging very large capacitors may
cause the current limit to increase slightly. In either case,
once the output voltage reaches its final value, the input
current limit will be restored to its nominal value.
If the load capacitor is too large there can be an additional
problem with inadvertent power shutdown by the PSE.
Consider the following scenario. If the PSE is running at
APPLICATIO S I FOR ATIO
WUUU
57V (maximum allowed) and the PD has been detected
and powered up, the load capacitor will be charged to
nearly – 57V. If for some reason the PSE voltage suddenly
is reduced to – 44V (minimum allowed), the input diodes
will reverse bias and PD power will be supplied solely by
the load capacitor. Depending on the size of the load
capacitor and the DC load of the PD, the PD will not draw
any power from the PSE for a period of time. If this period
of time exceeds the IEEE 802.3af 300ms disconnect
delay, the PSE may remove power from the PD. For this
reason, it is necessary to evaluate the load capacitance
and load current to ensure that inadvertent shutdown
cannot occur.
Maintain Power Signature
In an IEEE 802.3af system, the PSE uses the
maintain
power signature
(MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25k in parallel with 0.05µF. The PD application
circuits shown in this data sheet meet the requirements
necessary to maintain power. If either the DC current is
less than 10mA or the AC impedance is above 26.25k,
the PSE might disconnect power. The DC current must be
less than 5mA and the AC impedance must be above 2M
to guarantee power will be removed.
LTC4257
17
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APPLICATIO S I FOR ATIO
WUUU
Layout
The LTC4257 is relativity immune to layout problems.
Excessive parasitic capacitance on the R
CLASS
pin should
be avoided. If using the DD package, include an electrically
isolated heat sink to which the exposed pad on the bottom
of the package can be soldered. For optimal thermal
performance, make the heat sink as large as possible.
Voltages in a PD can be as large as –57V, so high voltage
layout techniques should be employed.
The load capacitor connected between Pins 5 and 8 of the
LTC4257 can store significant energy when fully charged.
The design of a PD must ensure that this energy is not
inadvertently dissipated in the LTC4257. The polarity-
protection diode(s) prevent an accidental short on the
cable from causing damage. However, if the V
IN
pin is
shorted to the GND pin inside the PD while the load
capacitor is charged, current will flow through the para-
sitic body diode of the internal MOSFET and may cause
permanent damage to the LTC4257.
Input Surge Suppression
The LTC4257 is specified to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily V
IN
and GND) can routinely
see peak voltages in excess of 10kV. To protect the
LTC4257, it is highly recommended that a transient volt-
age suppressor be installed between the bridge and the
LTC4257 (D3 in Figure 2).
LTC4257
18
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TYPICAL APPLICATIO
U
1
5
4
1
3
2
RX
SPARE
6
RX
+
3
TX
2
TX
+
J2
IN
FROM
PSE
T1
RJ45
1
7
8
5
4
6
8
7
TXOUT
+
OUT
TO PHY
TXOUT
SPARE
+
RXOUT
+
RXOUT
16
14
15
11
9
10
C19
47pF
C13
470pF
V
OUT
+
V
OUT
R24
100k
R28
10k
R23
3.65k
1%
R13
30.1k
1%
R17
10k
R14
100k
R11
10k
R10
62k
R25
62k
R26
10k
R27
62k
C20
0.47µF
C21
0.1µF
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE 5%
2. ALL CAPACITORS ARE 25V
3. SELECT R
CLASS
FOR CLASS 1-4 OPERATION. REFER
TO DATA SHEET APPLICATIONS INFORMATION SECTION
4. CONNECT TO CHASSIS GROUND
C4 TO C6: TDK C4532X5R0J107M
C2, C23: AVX 1808GC102MAT
D1, D7: MM3Z12VT1
D3: MMBD1505
D9 TO D12, D14 TO D16: DIODES INC., B1100
L1: COILCRAFT D01608C-472
T1: PULSE H2019
T2: PULSE PB2134
T3: PULSE PA0184
OSCAP SFSTt
ON
ENDLYMINENAB
LT1737CGN
R
OCMP
V
CC
R
CMPC
UVLO GATE
SGND PGND
V
C
FB
3V
OUT
I
SENSE
C22
680pF
0603
D8
BAT54
D5
B0540W
C17
3300pF
R15
0.22
1/2W
1%
R4
10k
T2
SEPARATING
LINE
FOR GROUND
PLANE
T3
8
D7
12V
1
C12
0.1µF
50V
C10
4.7µF
35V
R16
330
C16
0.1µF
50V
C23
1000pF
2kV
9
10
3
5
4
C18
1nF
R18
100
Q6
Si7892DP
Q7
FMMT718
Q8
MMBT3904
8
11
C14
1µF
R12
47
C4 TO C6
100µF
6.3V
3.3V @ 2.8A
Q3
Si4490DY
LTC4257CDD
R
CLASS
1%
NC
R
CLASS
NC
V
IN
GND
NC
PWRGD
V
OUT
C1B
0.82µF
100V
C1C
0.82µF
100V
L1
4.7µH
Q2
MMBT3904
Q4
MMBT2907ALT1
Q5
MMBT3904
R9
100
R8
47
R6
47
C9
100pF
D2
BAT54
Q1
MMBTA06
D4
BAS21LT1
D1
12V
D3A D3B
R7
33
1/4W
C1A
10µF
100V
R5
47K
+
Q9
2N7002
D13
MMSD4148
C11
0.1µF
100V
D6
SMAJ58A
R30
75
C24
0.01µF
200V
R31
75
C25
0.01µF
200V
R1
75
C7
0.01µF
200V
R2
75
C3
0.01µF
200V
C2
1000pF
2kV
4257 TA04
D10
B1100
D12
B1100
D9
B1100
D11
B1100
D17
B1100
D16
B1100
D15
B1100
D14
B1100
3
4
4
Figure 11: PD Power Interface with 3.3V, 2.8A High Efficiency Isolated Power Supply

LTC4257IS8#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE 802.3af PD Pwr over E Int Cntr
Lifecycle:
New from this manufacturer.
Delivery:
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