Si5350B
6 Rev. 0.9
Table 5. Output Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Units
Frequency Range FCLK 0.008 — 160 MHz
Load Capacitance C
L
F
CLK
< 100 MHz — — 15 pF
Duty Cycle DC Measured at V
DD
/2 45 50 55 %
Rise/Fall Time t
r
/t
f
20% - 80%, C
L
= 5 pF 0.5 1 1.5 ns
Output High Voltage VOH V
DD
– 0.6 — — V
Output Low Voltage VOL — — 0.6 V
Period Jitter JPER
Measured over 10k cycles
— 60 100 ps pk-pk
Period Jitter, VCXO JPER_VCXO — 60 110 ps pk-pk
Cycle-to-Cycle Jitter JCC
Measured over 10k cycles
—5090ps pk
Cycle-to-Cycle Jitter,
VCXO
JCC_VCXO — 50 95 ps pk
RMS Phase Jitter JRMS
12 kHz–20 MHz
—3.511 ps
RMS Phase Jitter JRMS_VCXO — 8.5 18.5 ps rms
Table 6. 25 MHz Crystal Requirements
1,2
Parameter Symbol Min Typ Max Unit
Crystal Frequency f
XTAL
—25—MHz
Load Capacitance C
L
6—12pF
Equivalent Series Resistance r
ESR
——150
Crystal Max Drive Level d
L
——100µW
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors. Adding external 2 pF load
capacitors can minimize jitter by 20%.
2. Refer to “AN551: Crystal Selection Guide” for more details.
