DS1672
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Data valid: The state of the data line represents valid data when, after a START condition, the
data line is stable for the duration of the high period of the clock signal. The data on the line must
be changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition.
The number of data bytes transferred between the START and the STOP conditions is not limited,
and is determined by the master device. The information is transferred byte-wise and each
receiver acknowledges with a ninth bit. Within the I
2
C bus specifications a standard mode
(100kHz clock rate) and a fast mode (400kHz clock rate) are defined.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device must generate an extra clock pulse that is
associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related
clock pulse. Of course, setup and hold times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master
to generate the STOP condition.
Figures 7 and 8 detail how data transfer is accomplished on the I
2
C bus. Depending upon the state of the
R/W bit, two types of data transfer are possible:
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1672 can operate in the following two modes:
1) Slave receiver mode (DS1672 write mode): Serial data and clock are received through SDA and
SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction bit (Figure 7). The slave address byte is the
first byte received after the START condition is generated by the master. The slave address byte
contains the 7-bit DS1672 address, which is 1101000, followed by the direction bit (R/W), which for
a write is a 0. After receiving and decoding the slave address byte the DS1672 outputs an
acknowledge on the SDA line. After the DS1672 acknowledges the slave address + write bit, the
master transmits a word address to the DS1672. This will set the register pointer on the DS1672, with
the DS1672 acknowledging the transfer. The master may then transmit zero or more bytes of data,
