ICS874003D-02 Data Sheet JITTER ATTENUATOR
ICS874003DG-02 REVISION A MARCH 11, 2016 4 ©2016 Integrated Device Technology, Inc.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance,
JA
86.7°C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage V
DD
– 0.15 3.3 V
DD
V
V
DDO
Output Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 80 mA
I
DDA
Analog Supply Current 15 mA
I
DDO
Output Supply Current 75 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High
Current
OEA, OEB V
DD
= V
IN
= 3.465V 5 µA
MR,
F_SEL[2:0]
V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low
Current
OEA, OEB V
DD
= 3.465V, V
IN
= 0V -150 µA
MR,
F_SEL[2:0]
V
DD
= 3.465V, V
IN
= 0V -5 µA
ICS874003D-02 Data Sheet JITTER ATTENUATOR
ICS874003DG-02 REVISION A MARCH 11, 2016 5 ©2016 Integrated Device Technology, Inc.
Table 4C. Differential DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4D. LVDS DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Table 5. AC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High
Current
CLK V
DD
= V
IN
= 3.465V 150 µA
nCLK V
DD
= V
IN
= 3.465V 5 µA
I
IL
Input Low
Current
CLK V
DD
= 3.465V, V
IN
= 0V -5 µA
nCLK V
DD
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Voltage;
NOTE 1
0.15 1.3 V
V
CMR
Common Mode Input
Voltage; NOTE 1, 2
GND + 0.5 V
DD
– 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage 275 375 485 mV
V
OD
V
OD
Magnitude Change 50 mV
V
OS
Offset Voltage 1.2 1.35 1.5 V
V
OS
V
OS
Magnitude Change 50 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 98 320 MHz
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 30 ps
tsk(o) Output Skew; NOTE 2, 3 185 ps
tsk(b) Bank Skew; NOTE 1, 4 Bank A 65 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 700 ps
odc Output Duty Cycle 47 53 %
ICS874003D-02 Data Sheet JITTER ATTENUATOR
ICS874003DG-02 REVISION A MARCH 11, 2016 6 ©2016 Integrated Device Technology, Inc.
Parameter Measurement Information
3.3V LVDS Output Load Test Circuit
Bank Skew
Output Skew
Differential Input Level
Cycle-to-Cycle Jitter
Output Duty Cycle/Pulse Width/Period
3.3V ±5%
V
DDA
V
DD,
V
DDO
tsk(b)
nQA0
QA0
nQA1
QA1
nQx
Qx
nQy
Qy
V
DD
nCLK
CLK
GND
V
CMR
Cross Points
V
PP
tcycle n tcycle n+1
tjit(cc) =
|
tcycle n – tcycle n+1
|
1000 Cycles
nQA[0:1],
nQB0
QA[0:1],
QB0
nQA[0:1],
nQB0
QA[0:1],
QB0

874003DG-02LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PCI EXPRESS JITTER ATTENUATOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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