NVMFD5489NLT1G

NVMFD5489NL
www.onsemi.com
4
TYPICAL CHARACTERISTICS
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V) Q
g
, TOTAL GATE CHARGE (nC)
50403020 60100
0
100
200
300
400
500
600
141086420
0
1
3
4
5
7
9
10
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
R
G
, GATE RESISTANCE ()
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
100101
1
10
100
1000
0.80.60.50.40.30.20.10
0
1
3
4
5
7
9
10
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
1001010.1
0.01
0.1
1
10
100
C, CAPACITANCE (pF)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
t, TIME (ns)
I
S
, SOURCE CURRENT (A)
I
D
, DRAIN CURRENT (A)
T
J
= 25°C
V
GS
= 0 V
C
iss
C
oss
C
rss
2
6
8
T
J
= 25°C
V
DD
= 48 V
V
GS
= 10 V
I
D
= 6 A
QT
Q
gs
V
DD
= 48 V
V
GS
= 10 V
I
D
= 6 A
t
r
t
f
t
d(off)
t
d(on)
0.7 0.9
2
6
8
T
J
= 25°C
V
GS
= 0 V
T
C
= 25°C
V
GS
= 10 V
Single Pulse
R
DS(on)
Limit
Thermal Limit
Package Limit
10 s
100 s
1 ms
10 ms
dc
12
Q
gd
NVMFD5489NL
www.onsemi.com
5
TYPICAL CHARACTERISTICS
Figure 12. Thermal Response
PULSE TIME (sec)
0.010.001 100.0001 0.10.00001 10.000001
0.001
0.01
0.1
1
10
100
R(t) (°C/W)
100 1000
50% Duty Cycle
Single Pulse
20%
10%
5%
2%
1%
NVMFD5489NL
www.onsemi.com
6
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.27
0.75
1.40
3.70
4.56
8X
PITCH
6.59
4.84
1.00
DIMENSION: MILLIMETERS
2.30
4X
0.70
5.55
4X
0.56
2X
2.08
2X
M 3.25
h −−−
3.50
−−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA
.
1234
56
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D1
E1
h
D
E
B
A
0.20 C
0.20 C
2X
2X
DIM MIN
MILLIMETERS
A 0.90
A1 −−−
b 0.33
c 0.20
D 5.15 BSC
D1 4.70
D2 3.90
E 6.15 BSC
E1 5.70
E2 3.90
e 1.27 BSC
G 0.45
K 0.51
L 0.48
A
0.10 C
0.10 C
14
8
e
8X
D2
b1
E2
b
A0.10 B
C
0.05
C
L
DETAIL A
A1
c
4X
5
MAX
−−−
−−−
0.42
−−−
4.90
4.10
5.90
4.15
0.55
−−−
0.61
M
N 1.80 2.00
78
N
PIN ONE
IDENTIFIER
NOTE 7
NOTE 4
C
SEATING
PLANE
DETAIL A
NOTE 6
4X
K
NOTE 3
D3 1.50 1.70
b1 0.33 0.42
4X
D3
G
4X
DETAIL B
DETAIL B
ALTERNATE
CONSTRUCTION
K1 0.56 −−−
K1
3.75
12
_
MAX
1.10
0.05
0.51
0.33
5.10
4.30
6.10
4.40
0.65
−−−
0.71
2.20
1.90
0.51
−−−
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NVMFD5489NLT1G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
MOSFET Pwr MOSFET 60V 12A 65mOhm Dual N-CH
Lifecycle:
New from this manufacturer.
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