844004AGI-04 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 25, 2009
1
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™ C RYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
0
1
Phase
Detector
VCO
M = ÷32
OSC
÷4
÷1
0
1
0
1
0
1
0
1
GENERAL DESCRIPTION
The ICS844004I-04 is a 4 output LVDS
Synthesizer optimized to generate clock
frequencies for a variety of high performance
applications and is a member of the
HiPerClocks
TM
family of high performance
clock solutions from ICS. This device can select its input
reference clock from either a crystal input or a single-
ended clock signal. It can be configured to generate 4
outputs with individually selectable divide-by-one or
divide-by-four function via the 4 frequency select pins
(F_SEL[3:0]). The ICS844004I-04 uses ICS’ 3
rd
generation
low phase noise VCO technology and can achieve 1ps
or lower typical rms phase jitter. This ensures that it
will easily meet clocking requirements for SDH (STM-1/
STM-4/STM-16) and SONET (OC-3/OC12/OC-48). This
device is suitable for multi-rate and multiple port line
card applications. The ICS844004I-04 is conveniently
packaged in a small 24-pin TSSOP package.
FEATURES
• Four LVDS outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
• Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
• VCO range: 560MHz - 680MHz
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.71ps (typical)
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.51ps (typical)
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 5MHz): 0.75ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
HiPerClockS™
ICS
PIN ASSIGNMENT
ICS844004I-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQ1
Q1
V
DDo
Q0
nQ0
MR
F_SEL3
nc
V
DDA
F_SEL0
V
DD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
nQ2
Q2
V
DDO
Q3
nQ3
GND
F_SEL2
INPUT_SEL
CLK
GND
XTAL_IN
XTAL_OUT
24
23
22
21
20
19
18
17
16
15
14
13
BLOCK DIAGRAM
CLK
INPUT_SEL
MR
F_SEL0
F_SEL1
F_SEL2
F_SEL3
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
XTAL_IN
XTAL_OUT
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
