ZL30164GDG2

1
Microsemi Corporation
Copyright 2014, Microsemi Corporation. All Rights Reserved.
Features
Fully compliant SEC (G.813), EEC (G.8262) and
Stratum 3E flexible rate conversion DPLL
Three programmable digital PLLs/Numerically
Controlled Oscillators (NCOs)
Synchronize to any clock rate from 1 Hz to
750 MHz
Four programmable synthesizers generate any
clock rate from 1 Hz to 750 MHz with low jitter for
10G PHYs
Flexible two-stage architecture translates between
arbitrary data rates, line coding rates and FEC
rates
Digital PLLs filter jitter from 0.1 mHz up to 1 kHz
Automatic hitless reference switching and digital
holdover on reference fail
Nine input references configurable as single ended
or differential and two single ended input
references
Any input reference can be fed with sync (frame
pulse) or clock
Programmable DPLLs can synchronize to sync
pulse and sync pulse/clock pair
Eight LVPECL outputs and eight LVCMOS outputs
Operates from a single crystal resonator or clock
oscillator
Field programmable via SPI/I
2
C interface
Applications
SyncE/SONET/SDH Timing Cards
Synchronous Ethernet, 10 GBASE-R and
10 GBASE-W
SONET/SDH, Fibre Channel, XAUI
March 2014
Figure 1 - Functional Block Diagram
ZL30164
Triple Channel Network Synchronization
Clock Translator
Short Form Data Sheet
Ordering Information
ZL30164GDG2 144 Pin LBGA Trays
Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
Package Size: 13 x 13 mm
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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ZL30164GDG2

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products 10GbE Any Frequency Triple Channel DPLL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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