TCP−3027HA
www.onsemi.com
5
ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE
The following assembly considerations should be observed:
Cleanliness
These chips should be handled in a clean environment.
Electro-static Sensitivity
ON Semiconductor’s PTICs are ESD Class 1A sensitive.
The proper ESD handling procedures should be used.
Mounting
The QFN PTIC is fabricated for Flip Chip solder
mounting. The output pads are plated with pure tin, and the
device is rated as MSL2. The PTIC QFN is RoHS-compliant
and compatible with lead-free soldering profile.
Figure 6. Reflow Profile
Table 4. Reflow Profile Chart
Profile Feature Pb−Free Assembly
Average ramp−up rate (Ts
max
to T
p
) 3°C / second max
Preheat
Temperature Min (Ts
min
)
Temperature Max (Ts
max
)
Time (Ts
min
to Ts
max
) (ts)
150°C
200°C
60−180 seconds
Time maintained above
Temperature (T
L
)
Time (t
L
)
217°C
60−150 seconds
Peak Temperature (Tp) 260°C (maximum for
the customer)
Time within 5°C of actual Peak
Temperature (tp)
2
20−40 seconds
Ramp−down Rate 6°C / second max
Time 25°C to Peak Temperature 8 minutes max
ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES
When configuring the PTIC in your specific circuit
design, at least one of the RF terminals must be connected
to DC ground. If minimum transition times are required, DC
ground on both RF terminals is recommended. To minimize
losses, the PTIC should be oriented such that RF2
is at the
lower RF impedance of the two RF nodes. A shunt PTIC, for
example, should have RF2
connected to RF ground.
Figure 7. PTIC Orientation Functional Block
Diagram
Bias
RF ANT
RF1
(PTIC Pad)
RF2
(PTIC Pad)
