Features
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Freescale Semiconductor 9
– Eliminates the need to copy data from a source context into a kernel context, change to
destination address space, then copy the data to the destination address space or alternatively
to map the user space into the kernel address space
3.6.2 512-Kbyte Private Backside Cache
• Each e5500 core features a 512-Kbyte private backside L2 cache running at the same frequency of
CPU. The caches support:Write Back, pseudo LRU replacement algorithm
• Tag parity and ECC data protection
• Eight-way, with arbitrary partitioning between instruction and data. For example, 3-ways
instruction, 5-ways data, and so on.
• Supports direct stashing of datapath architecture data into cache
3.6.3 CoreNet Platform Cache (CPC)
The QorIQ P5020 also contains 2x1-Mbyte of shared CoreNet platform cache, with the following features:
• Configurable as write back or write through
• Pseudo LRU replacement algorithm
• ECC protection
• 64-byte coherency granule
• Two cache line read 1024 bits per cycle at 800 MHz, 32-way cache array configurable to any of
several modes on a per-way basis
— Unified cache, I-only, D-only
— I/O stash (configurable portion of each packet copied to CPC on write to main memory)
– Stashing of all transactions and sizes supported
– Explicit (CoreNet signalled) and implicit (address range based) stash allocation
— Addressable SRAM (32-Kbyte granularity)
3.6.4 CoreNet Fabric and Address Map
The CoreNet fabric is Freescale’s next generation Interconnect Standard for multicore products, and
provides the following:
• A highly concurrent, fully cache coherent, multi-ported fabric
• Point-to-point connectivity with flexible protocol architecture allows for pipelined interconnection
between CPUs, platform caches, memory controllers, and I/O and accelerators at up to 800 MHz
• The CoreNet fabric has been designed to overcome bottlenecks associated with shared bus
architectures, particularly address issue and data bandwidth limitations. The P5020’s multiple,
parallel address paths allow for high address bandwidth, which is a key performance indicator for
large coherent multicore processors
• Eliminates address retries, triggered by CPUs being unable to snoop within the narrow snooping
window of a shared bus. This results in the device having lower average memory latency