CY62256V
Document #: 38-05057 Rev. *F Page 5 of 12
Switching Characteristics Over the Operating Range
[7]
Parameter Description
CY62256V-70
UnitMin. Max.
Read Cycle
t
RC
Read Cycle Time 70 ns
t
AA
Address to Data Valid 70 ns
t
OHA
Data Hold from Address Change 10 ns
t
ACE
CE LOW to Data Valid 70 ns
t
DOE
OE LOW to Data Valid 35 ns
t
LZOE
OE LOW to Low-Z
[8]
5ns
t
HZOE
OE HIGH to High-Z
[8, 9]
25 ns
t
LZCE
CE LOW to Low-Z
[8]
10 ns
t
HZCE
CE HIGH to High-Z
[8, 9]
25 ns
t
PU
CE LOW to Power-up 0 ns
t
PD
CE HIGH to Power-down 70 ns
Write Cycle
[10, 11]
t
WC
Write Cycle Time 70 ns
t
SCE
CE LOW to Write End 60 ns
t
AW
Address Set-up to Write End 60 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Set-up to Write Start 0 ns
t
PWE
WE Pulse Width 50 ns
t
SD
Data Set-up to Write End 30 ns
t
HD
Data Hold from Write End 0 ns
t
HZWE
WE LOW to High-Z
[8, 9]
25 ns
t
LZWE
WE HIGH to Low-Z
[8]
10 ns
Notes:
7. Test conditions assume signal transition time of 5 ns or less timing reference levels of V
CC
/2, input pulse levels of 0 to V
CC
, and output loading of the specified
I
OL
/I
OH
and 50 pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
10.The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
[+] Feedback
