PC56F84789VLL Datasheet MC56F84543VLH, MC56F84565VLK, MC56F84567VLL | P10-P12

• Channels not used for PWM generation can be used for input capture functions

• Enhanced dual edge capture functionality

• Synchronization to external hardware or other PWM supported

• Double buffered PWM registers

• Integral reload rates from 1 to 16

• Half-cycle reload capability

• Multiple output trigger events can be generated per PWM cycle via hardware

• Support for double switching PWM outputs

• Up to eight fault inputs can be assigned to control multiple PWM outputs

• Programmable filters for fault inputs

• Independently programmable PWM output polarity

• Individual software control of each PWM output

• All outputs can be programmed to change simultaneously via a FORCE_OUT event

• PWMX pin can optionally output a third PWM signal from each submodule

• Option to supply the source for each complementary PWM signal pair from any of the following:

• Crossbar module outputs

• External ADC input, taking into account values set in ADC high and low limit registers

3.7.3.2 Quad Timer

• Four 16-bit up/down counters with programmable prescaler for each counter

• Operation modes: edge count, gated count, signed count, capture, compare, PWM, signal shot, single pulse, pulse

string, cascaded, quadrature decode

• Programmable input filter

• Counting start can be synchronized across counters

3.7.3.3 Enhanced Quadrature Decoder

• Includes logic to decode quadrature signals

• Configurable digital filter for inputs to remove glitches and ensure only true transitions are recorded

• 32-bit position counter register

• 16-bit position difference register

• Maximum count frequency equals the IPBus clock rate

• Position counter can be initialized by software or external events

• Position counter and resolution counter can be captured by external trigger signal (new feature)

• Preloadable 16-bit revolution counter

• Inputs can be connected to a general purpose timer, aiding low speed velocity measurements

• Watchdog timer to detect a non-rotating shaft condition

• Optional use as a single phase pulse accumulator

3.7.3.4 Periodic Interrupt Timer (PIT) Modules

• 16-bit up-counter with programmable counter modulo

• Interrupt capability

• Selectable clock sources:

• External crystal oscillator/external clock source

• On-chip low-power 32 kHz oscillator

• System bus (IPBus up to 100 MHz)

• 8 MHz / 400 kHz ROSC

• Can signal the device to exit powerdown mode

• Programmable master/slave selection between PIT instances

3.7.3.5 Programmable Delay Block (PDB) Modules

• 16-bit counter with programmable counter modulo and delay time

Timers and PWM modules

MC56F844x/5x/7x Product Brief, Rev. 2, 06/2012

10 Freescale Semiconductor, Inc.

General Business Information

• Counter is initiated by positive transition of internal or external trigger pulse

• Support for synchronizing PWM and ADC conversions

• Two PDB outputs can be ORed together to schedule two conversions from one input trigger event

• PDB outputs can be used to schedule precise edge placement for a pulsed output that generates the control signal for

the CMP windowing comparison

• Support for continuous mode or single shot mode

• Bypass mode supported

3.7.3.6 Computer Operating Properly (COP) Watchdog

• Programmable timeout period

• Support for operation in all power modes: run mode, wait mode, stop mode

• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected

• Selectable reference clock source in support of EN60730 and IEC61508

• Selectable clock sources:

• External crystal oscillator/external clock source

• On-chip low-power 32 kHz oscillator

• System bus (IPBus up to 100 MHz)

• 8 MHz / 400 kHz ROSC

• Support for interrupt triggered when the counter reaches the timeout value

3.7.3.7 External Watchdog Monitor (EWM)

• Monitors external circuit as well as the software flow

• Programmable time-out period

• Interrupt capability prior to time-out

• Independent output (EWM_OUT_b) that places external circuit (but not CPU and peripheral) in a safe mode when

EWM time-out occurs

• Selectable reference clock source in support of EN60730 and IEC61508

• Wait mode and stop mode operation is not supported

• Selectable clock sources:

• External crystal oscillator/external clock source

• On-chip low-power 32 kHz oscillator

• System bus (IPBus up to 100 MHz)

• 8 MHz / 400 kHz ROSC

Clock Modules

3.7.4.1 On-Chip Oscillators

• Tunable 8 MHz relaxation oscillator with 400 kHz at standby mode (divide-by-two output)

• 32 kHz low frequency clock as secondary clock source for COP, EWM, PIT

3.7.4.2 Crystal Oscillator

• Support for both high ESR crystal oscillator (greater than 100-ohm ESR) and ceramic resonator

• 4 MHz to 16 MHz operating frequency

3.7.4.3 Phase Locked Loop

• Wide programmable output frequency: 240 MHz to 400 MHz

• Input reference clock frequency: 8 MHz to 16 MHz

3.7.4

Clock Modules

MC56F844x/5x/7x Product Brief, Rev. 2, 06/2012

Freescale Semiconductor, Inc. 11

General Business Information

• Detection of loss of lock and loss of reference clock

• Ability to power down

Analog Modules

3.7.5.1 12-bit Analog-to-Digital Converter (Cyclic type)

• Two independent 12-bit analog-to-digital converters (ADCs)

• 2 x 8-channel external inputs

• Built-in x1, x2, x4 programmable gain pre-amplifier

• Maximum ADC clock frequency is up to 20 MHz with 50 ns period

• Single conversion time of 8.5 ADC clock cycles (8.5 x 50 ns = 425 ns)

• Additional conversion time of 6 ADC clock cycles (6 x 50 ns = 300 ns)

• Sequential, parallel, and independent scan mode

• First 8 samples have offset, limit and zero-crossing calculation supported

• ADC conversions can be synchronized by any module connected to internal crossbar module, such as PWM and timer

modules and GPIO and comparators

• Support for simultaneous and software triggering conversions

• Support for multi-triggering mode with a programmable number of conversions on each trigger

• Each ADC has ability to scan and store up to 8 conversion results

3.7.5.2 16-bit Analog-to-Digital Converter (SAR type)

• Linear successive approximation algorithm with up to 16-bit resolution

• Differential and 16 single-ended external analog inputs

• Maximum ADC clock frequency up to 12.5 MHz

• Output modes: single-ended 16-bit, 12-bit, 10-bit, and 8-bit modes

• Output formatted in 2's complement, 16-bit sign extended for differential modes

• Output in right-justified, unsigned format for single-ended modes

• Single or continuous conversion (automatic return to idle after single conversion)

• Configurable sample time and conversion speed/power

• Conversion complete / hardware average complete flag and interrupt

• Input clock selectable from up to four sources

• Operation in low-power modes for lower-noise operation

• Asynchronous clock source for lower-noise operation with option to output the clock

• Automatic compare with interrupt for less-than, greater-than, or equal-to, within range or out-of-range programmable

value

• Integrated temperature sensor

• Selectable voltage reference: internal, external, or alternate

3.7.5.3 12-bit Digital-to-Analog Converter

• 12-bit resolution

• Powerdown mode

• Automatic mode allows the DAC to generate its own output waveforms including square, triangle, and sawtooth

waveforms

• Programmable period, update rate, and range

• Output can be routed to internal comparator, ADC, or optionally off chip

3.7.5.4 6-bit Digital-to-Analog Converter

• 2.7 V to 3.3 V operation range

• 64-tap resistor ladder

3.7.5

Analog Modules

MC56F844x/5x/7x Product Brief, Rev. 2, 06/2012

12 Freescale Semiconductor, Inc.

General Business Information

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

PC56F84789VLL

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Digital Signal Processors & Controllers - DSP, DSC 32BIT,256K FLASH,2KB FLEX

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PC56F84789VLL

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