FXO-PC72 Series
Page 6 of 15
© 2008 FOX ELECTRONICS | ISO9001:2000 Certified
NOTE: XPRESSO LVPECL XOs are designed to
fit on Industry Standard, 6 pad layouts
Pin Description and Recommended Circuit
Pin #
Name
Type
Function
1
E / D
1
Logic Enable / Disable Control of Output (0 = Disabled)
2
NC
2
No Connection – Leave OPEN
3 GND Ground Electrical Ground for V
DD
4 Output Output LVPECL Oscillator Output
5 Output 2 Output Complementary LVPECL Output
6
V
DD
3
Power Power Supply Source Voltage
NOTES:
1
Includes pull-up resistor to V
DD
to provide output when the pin (1) is No Connect. (Also see note 2)
2
An optional pin # 2 Enable / Disable is available.
3
Installation should include a 0.01µF bypass capacitor placed between V
DD
(Pin 6) and GND (Pin 3) to minimize power supply line noise.
E / D V
DD
NC Output 2
GND Output
Terminations as viewed from the Top
Enable / Disable Control
Pin # 1 (state) Output (Pin # 4, Pin # 5)
OPEN
(No Connection)
ACTIVE Output
“1” Level V
IH
> 70% V
DD
ACTIVE Output
“0” Level V
IL
< 30% V
DD
High Impedance
3
1
4
6
Soldering Reflow Profile (2 times Maximum at 260°C for 10 seconds MAX)
25°C
160°C
180°C
225°C
260°C
10 Seconds Max
within 5°C of 260°C peak
Ramp Down
Not to exceed 6°C/s
Ramp-Up
3°C/s Max
p
t
120 ± 20 Seconds
In Pre-heating Area
Above 225°C Reflow Area
50±10 Seconds
400 Seconds MAX from +25°C to 260°C peak
2
5
LVPECL OUT#2
0.01μF
LVPECL OUT
# 3
GND
# 4
E/D
N C
# 1
# 2
# 6
# 5
DD
V
50Ώ
V
DD
- 2V
50Ώ
0.01μF
