Functional description L5951
6/18 DocID7510 Rev 2
Waveshaping - Messages sent by the microcontroller to the transceiver are routed to a
waveshaping circuit. The digital signal is rounded at the switching points in order to reduce
EMI emissions. A second order function, I = C*dV/dt, is used to control the rise and fall times
of the transmission. The rise and fall times are controlled by an external resistor Rext. The
waveshaping circuit can be enabled and disabled by the 4X pin. A logic "1" will disable the
waveshape circuit and a logic "0" will enable the waveshape circuit. In 4X mode, the speed
of the BUS is increased by a factor of four. Any signal coming from the microcontroller and
going to the BUS must be waveshaped. If loopback (LOOP) is enabled, the signal coming
from the micro through the TX pin is routed to the RX pin back to the micro with or without it
being waveshaped. A logic "1" enables loopback and a logic "0" disables loopback.
Nodes - The transmitter provides a wave-shaped 0 to 7.7 VDC waveform on the BUS
output. It also receives waveforms and transmits a digital level signal back to a logic IC. The
transmitter can drive up to 32 remote transceivers. These remote nodes may be at ground
potentials that are ±2 VDC, with respect to the assembly. Under this condition, waveshaping
will only be maintained during 3 of the 4 corners. The L5951 is a remote node on the Class
2/IDR Bus. Each remote transceiver has a 470 + 10% pF capacitor on its output for EMI
suppression, as well as a 10.6 k + 5% pull down resistor to ground. The main node has a
3.300 + 10% pF capacitor on its output for EMI suppression, as well as a 1.5 k + 5% pull
down resistor to ground. With more than 26 nodes there is no primary node, all nodes will
have the 470 ±10% pF capacitor and the 10.6k 5% pull down resistor. No matter how
many remote nodes are on the Class 2/IDR Bus, the RC of the Class 2/IDR Bus is
maintained at approximately 5ms. The minimum and maximum load on the Class 2/IDR Bus
is given below:
2.5 Protection
The L5951 can survive under the following conditions: shorting the outputs to BAT and
GND, loss of BAT, loss of IC GND, double battery(+26.5V), 4000V ESD, 34V load dump.
L5951 will not handle a reverse battery condition. External components must be
implemented for reverse battery protection.
Thermal Shutdown: thermal shutdown is broken down into two areas; V1 and V2 pouts,
and the other is V3 output and the Class 2 Bus Driver. V1 and V2 outputs shutdown at
160°C and returns to normal operation at 130°C. The V3 output and Class 2 Bus Driver
shutdown at 150°C and return to normal operation at 120°C.
Current Limiting: each voltage regulator will contain its own current protection, and the
maximum allowable current for all three regulators is 280mA.
Short Circuit: If the outputs are short circuited, the IC will begin current limiting and
eventually the thermal shutdown will kick in. Current limiting will not disable the outputs.
Overvoltage: The IC will not operate if the BAT voltage reaches 30V or above. V1 and V2
will not be shutdown, but all other outputs will not operate.
Loss of Ground & Loss of Battery Connection: in this conditions a very small leakage on
BUS is generated.
Table 3. Minimum and maximum load on the Class 2/IDR Bus
Capacitance Resistance to ground
Minimum Nodes (3.33 · .9) + (.47 · .9) = 3.39 nF (1.5 · 1.05) || (10.6 · 1.05) = 1.38 k
Maximum Nodes (3.3 · 1.1) + 25·(0.47 · 1.1) = 16.55 nF (1.5 · 0.95) || (10.6 · 0.95) / 25 = 314
Obsolete Product(s) - Obsolete Product(s)
