3
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVN16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
PIN DESCRIPTION
Pin Names Description
Q1 - Q13 Data Output
GND Ground
VDDQ Output-stage drain power voltage
VDD Logic power voltage
RESET Asynchronous reset input - resets registers and disables data and clock differential input recievers
VREF Input reference voltage
CLK Positive master clock input
CLK Negative master clock input
D1 - D13 Data Input - clocked in on the crossing of the rising edge of CLK and the falling edge of CLK
Center PAD Ground (MLF package only)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIK Control Inputs VDD = 2.3V, II= −18mA — — –1.2 V
VOH VDD = 2.3V to 2.7V, IOH = -100μAVDD – 0.2 — — V
VDD = 2.3V, IOH = -8mA 1.95 — —
V
OL VDD = 2.3V to 2.7V, IOL = 100μA — — 0.2 V
VDD = 2.3V, IOL = 8mA — — 0.35
II All Inputs VDD = 2.7V,VI = VDD or GND — — ±5 μA
I
DD Static Standby IO = 0, VDD = 2.7V, RESET = GND — — 0.01 mA
Static Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC) ——20
Dynamic Operating (Clock Only) I
O = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),—6—μA/Clock
CLK and CLK Switching 50% Duty Cycle. MHz
IDDD Dynamic Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),—43—μA/Clock
(Per Each Data Input)
(1)
CLK and CLK Switching 50% Duty Cycle. One Data Input MHz/Data
Switching at Half Clock Frequency, 50% Duty Cycle. Input
Data Inputs VDD = 2.5V, VI = VREF ± 310mV 2 — 3
C
I CLK and CLK VICR = 1.25V, VI (PP) = 360mV 2 — 3 pF
RESET V
I = VDD or GND 2 — 3
NOTE:
1. Power dissipation levels will allow operation at DDR333 speeds without excessive die temperature.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC1600 -
PC2700
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDD = 2.5V ±0.2V, VDDQ = 2.5V ±0.2V
