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MAX1003CAX

P1-P3P4-P6P7-P9P10-P12
For applications where a DC component of the input
signal is present, Figures 4 and 5 show single-ended
and differential DC-coupled input circuits. The ampli-
fiers’ input common-mode voltage range extends from
1.75V to 2.75V. To prevent attenuation of the input
signal’s DC component in this mode, disable the offset-
correction amplifier by grounding the _OCC+ and
_OCC- pins for the I and Q blocks (Figures 4 and 5).
ADCs
The I and Q ADC blocks receive the analog signals
from the respective I and Q input amplifiers. The ADCs
use flash conversion with 63 fully differential compara-
tors to digitize the analog input signal into a 6-bit output
in offset binary format.
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________ 7
Figure 2. Single-Ended AC-Coupled Input
Figure 3. Differential AC-Coupled Input
Figure 4. Single-Ended DC-Coupled Input
Figure 5. Differential DC-Coupled Input
MAX1003
INPUT
AMP
20k
2.35V INTERNAL REFERENCE
20k
_IN+
_OCC+ _OCC-
_IN-
0.1µF
0.1µF
V
SOURCE
OFFSET
CORREC-
TION
0.22µF
MAX1003
INPUT
AMP
20k
2.35V INTERNAL REFERENCE
20k
_IN+
_OCC+ _OCC-
_IN-
OFFSET CORRECTION DISABLED
V
SOURCE
V
REF
1.75V TO 2.75V
OFFSET
CORREC-
TION
MAX1003
INPUT
AMP
20k
2.35V INTERNAL REFERENCE
20k
_IN+
_OCC+ _OCC-
_IN-
OFFSET CORRECTION DISABLED
V
SOURCE
DIFFERENTIAL SOURCE
WITH COMMON MODE
FROM 1.75V TO 2.75V.
OFFSET
CORREC-
TION
MAX1003
The MAX1003 features a proprietary encoding scheme
that ensures no more than 1LSB dynamic encoding
error. Dynamic encoding errors resulting from
metastable states may occur when the analog input
voltage, at the time the sample is taken, falls close to
the decision point for any one of the input comparators.
The resulting output code for typical converters can be
incorrect, including false full- or zero-scale outputs. The
MAX1003’s unique design reduces the magnitude of
this type of error to 1LSB.
Internal Voltage Reference
An internal buffered bandgap reference is included on
the MAX1003 to drive the ADCs’ reference ladders. The
on-chip reference and buffer eliminate any external
(high-impedance) connections to the reference ladder,
minimizing the potential for noise coupling from exter-
nal circuitry while ensuring that the voltage reference,
input amplifier, and reference ladder track well with
variations of temperature and power supplies.
Oscillator Circuit
The MAX1003 includes a differential oscillator, which is
controlled by an external parallel resonant (tank) net-
work as shown in Figure 6. Alternatively, the oscillator
may be overdriven with an external clock source as
shown in Figure 7.
Internal Clock Operation (Tank)
If the tank circuit is used, the resonant inductor should
have a sufficiently high Q and a self-resonant frequen-
cy (SRF) of at least twice the intended oscillator fre-
quency. Coilcraft’s 1008HS-221, with an SRF of
700MHz and a Q of 45, works well for this application.
Generate different clock frequency ranges by adjusting
varactor and tank elements.
An internal clock-driver buffer is included to provide
sharp clock edges to the internal flash comparators.
The buffer ensures that the comparators are simultane-
ously clocked, maximizing the ADCs’ effective number
of bits (ENOB) performance.
Low-Power, 90Msps, Dual 6-Bit ADC
8 _______________________________________________________________________________________
Figure 6. Tank Resonator Oscillator
Figure 7. External Clock Drive Circuit
MAX1003
CLK
DRIVER
TNK-
V
CLK
V
CLK
= 300mV
p-p
TO 1.25V
p-p
TNK+
50Ω
50Ω
Z
0
= 50Ω
50Ω
0.1µF
0.1µF
External Clock Operation
To accommodate designs that use an external clock,
the MAX1003’s internal oscillator can be overdriven by
an external clock source as shown in Figure 7. The
external clock source should be a sinusoid to minimize
clock phase noise and jitter, which can degrade the
ADCs’ ENOB performance. AC couple the clock source
(recommended voltage level is approximately 1Vp-p) to
the oscillator inputs as shown in Figure 7.
Output Data Format
The conversion results are output on a dual, 6-bit-wide
data bus. Data is latched into the ADC output latch fol-
lowing a pipeline delay of one clock cycle, as shown in
Figure 8. Output data is clocked out of the respective
ADC’s data output pins (D_0 through D_5) on the rising
edge of the clock output (DCLK), with a DCLK-to-data
propagation delay (t
PD
) of 3.6ns. The MAX1003 outputs
are +3.3V CMOS-logic compatible.
Transfer Function
Figure 9 shows the MAX1003’s nominal transfer function.
Output coding is offset binary with 1LSB = FSR / 63.
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________ 9
Figure 9. Ideal Transfer Function
Figure 8. MAX1003 Timing Diagram
DATA OUT
1.4V
DATA VALID N - 1 DATA VALID N
1.4V
50%
t
SKEW
t
DCLK
t
AD
t
PD
TNK+
(INPUT CLOCK)
DCLK
ANALOG
INPUT
N
N + 1
N + 2
P1-P3P4-P6P7-P9P10-P12

MAX1003CAX

Mfr. #:
Buy MAX1003CAX
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC Low-Power, 90Msps, Dual 6-Bit ADC
Lifecycle:
New from this manufacturer.
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