LTC4069EDC-4.4#TRMPBF

LTC4069-4.4
13
406944fa
APPLICATIONS INFORMATION
Power Dissipation
The conditions that cause the LTC4069-4.4 to reduce charge
current through thermal feedback can be approximated
by considering the power dissipated in the IC. For high
charge currents, the LTC4069-4.4 power dissipation is
approximately:
P
D
= (V
CC
– V
BAT
) • I
BAT
where P
D
is the power dissipated, V
CC
is the input supply
voltage, V
BAT
is the battery voltage and I
BAT
is the charge
current. It is not necessary to perform any worst-case
power dissipation scenarios because the LTC4069-4.4
will automatically reduce the charge current to maintain
the die temperature at approximately 115°C. However, the
approximate ambient temperature at which the thermal
feedback begins to protect the IC is:
T
A
= 115°C – P
D
θ
JA
T
A
= 115°C – (V
CC
– V
BAT
) • I
BAT
θ
JA
Example: Consider an LTC4069-4.4 operating from a 5V
wall adapter providing 750mA to a 3.6V Li-Ion battery.
The ambient temperature above which the LTC4069-
4.4 will begin to reduce the 750mA charge current is
approximately:
T
A
= 115°C – (5V – 3.6V) • (750mA) • 60°C/W
T
A
= 115°C – (1.05W • 60°C/W) = 115°C – 63°C
T
A
= 52°C
The LTC4069-4.4 can be used above 70°C, but the
charge current will be reduced from 750mA. The
approximate current at a given ambient temperature can
be calculated:
I
CT
VV
BAT
A
CC BAT JA
=
°
()
115
–•θ
Using the previous example with an ambient temperature
of 73°C, the charge current will be reduced to
approximately:
I
CC
VV CW
C
CA
mA
BAT
=
°°
()
°
=
°
°
=
115 73
536 60
42
84
500
–. / /
Furthermore, the voltage at the PROG pin will change
proportionally with the charge current as discussed in
the Programming Charge Current section.
It is important to remember that LTC4069-4.4 applications
do not need to be designed for worst-case thermal
conditions since the IC will automatically limit power
dissipation when the junction temperature reaches
approximately 115°C.
Board Layout Considerations
In order to deliver maximum charge current under all
conditions, it is critical that the exposed metal pad on
the backside of the LTC4069-4.4 package is soldered to
the PC board copper and extending out to relatively large
copper areas or internal copper layers connected using
vias. Correctly soldered to a 2500mm
2
double-sided 1 oz.
copper board the LTC4069-4.4 has a thermal resistance
of approximately 60°C/W. Failure to make thermal contact
between the Exposed Pad on the backside of the package
and the copper board will result in thermal resistances far
greater than 60°C/W. As an example, a correctly soldered
LTC4069-4.4 can deliver over 750mA to a battery from
a 5V supply at room temperature. Without a backside
thermal connection, this number could drop to less than
500mA.
V
CC
Bypass Capacitor
Many types of capacitors can be used for input bypassing;
however, caution must be exercised when using multi-layer
ceramic capacitors. Because of the self-resonant and high
Q characteristics of some types of ceramic capacitors, high
voltage transients can be generated under some start-up
conditions, such as connecting the charger input to a live
power source. For more information, refer to Application
Note 88.
LTC4069-4.4
14
406944fa
Thermistors
The LTC4069-4.4 NTC trip points are designed to
work with thermistors whose resistance-temperature
characteristics follow Vishay Dale’s “R-T Curve 1.” The
Vishay NTHS0603N01N1003J is an example of such a
thermistor. However, Vishay Dale has many thermistor
products that follow the “R-T Curve 1” characteristic in a
variety of sizes. Furthermore, any thermistor whose ratio
of R
COLD
to R
HOT
is about 6 will also work (Vishay Dale R-T
Curve 1 shows a ratio of R
COLD
to R
HOT
of 3.266/0.5325
= 6.13).
Designers may want to use thermistors whose room
temperature value is different than 100k. Vishay Dale has
a number of values of thermistor from 32k to 100k that
follow the “R-T Curve 1.” Using different R-T curves, such
as Vishay Dale “R-T Curve 2”, is also possible. This curve,
combined with LTC4069-4.4 internal thresholds, gives
temperature trip points of approximately –3°C (falling) and
42°C (rising), a delta of 45°C. This delta in temperature
can be moved in either direction by changing the value of
R
NOM
with respect to R
NTC
. Increasing R
NOM
will move
both trip points to higher temperatures.
To calculate R
NOM
for a shift to lower temperature for
example, use the following equation:
R
R
RatC
NOM
COLD
NTC
3 266
25
.
where R
COLD
is the resistance ratio of R
NTC
at the desired
cold temperature trip point. If you want to shift the trip points
to higher temperatures use the following equation:
R
R
RatC
NOM
HOT
NTC
0 5325
25
.
where R
HOT
is the resistance ratio of R
NTC
at the desired
hot temperature trip point.
Here is an example using a 10k R-T Curve 2 thermistor
from Vishay Dale. The difference between the trip points
is 45°C, from before, and we want the cold trip point to
be 0°C, which would put the hot trip point at 45°C. The
R
NOM
needed is calculated as follows:
R
R
RatC
NOM
COLD
NTC
=
3 266
25
2 816
3
.
.
..
•.
266
10 8 62kk=
The nearest 1% value for R
NOM
is 8.66k. This is the value
used to bias the NTC thermistor to get cold and hot trip
points of approximately 0°C and 45°C respectively. To
extend the delta between the cold and hot trip points, a
resistor, R1, can be added in series with R
NTC
(see Figure
6). The values of the resistors are calculated as follows:
R
RR
R
NOM
COLD HOT
=
=
3 266 0 5325
0 5325
3 266
1
..
.
.
()
0 5325.
•R R R
COLD HOT HOT
where R
NOM
is the value of the bias resistor and R
HOT
and
R
COLD
are the values of R
NTC
at the desired temperature
trip points. Continuing the example from before with a
desired trip point of 50°C:
4069 F06
R
NOM
8.87k
R
NTC
10k
V
CC
+
+
+
TOO COLD
TOO HOT
NTC_ENABLE
R1
604Ω
0.76 • V
CC
0.35 • V
CC
0.016 • V
CC
6
NTC
Figure 6. NTC Circuits
APPLICATIONS INFORMATION
LTC4069-4.4
15
406944fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
R
RR
k
NOM
COLD HOT
=
=
3 266 0 5325
10 2 816 0
..
•. .
44086
3 266 0 5325
88 887
()
=
..
.,.kkis %.
.
.
the nearest value
Rk
1
10
0 5325
326
1
=
66 0 5325
2 816 0 408604086
()
.
•. . .
,%.= 604 604 1Ω is the nearest value
NTC Trip Point Error
When a 1% resistor is used for R
HOT
, the major error
in the 40°C trip point is determined by the tolerance of
the NTC thermistor. A typical 100k NTC thermistor has
±10% tolerance. By looking up the temperature coeffi cient
of the thermistor at 40°C, the tolerance error can be
calculated in degrees centigrade. Consider the Vishay
NTHS0603N01N1003J thermistor, which has a temperature
coeffi cient of –4%/°C at 40°C. Dividing the tolerance by
the temperature coeffi cient, ±5%/(4%/°C) = ±1.25°C, gives
the temperature error of the hot trip point.
The cold trip point error depends on the tolerance of the
NTC thermistor and the degree to which the ratio of its
value at 0°C and its value at 40°C varies from 6.14 to
1. Therefore, the cold trip point error can be calculated
using the tolerance, TOL, the temperature coeffi cient
of the thermistor at 0°C, TC (in %/°C), the value of the
thermistor at 0°C, R
COLD
, and the value of the thermistor
at 40°C, R
HOT
. The formula is:
Temperature Error C
TOL
R
R
COLD
HOT
()
.
°=
+1
614
1 100
TC
For example, the Vishay NTHS0603N01N1003J thermistor
with a tolerance of ±5%, TC of –5%/°C and R
COLD
/R
HOT
of 6.13, has a cold trip point error of:
Temperature Error C()
.
.
•.
°=
+
1005
614
613 1
100
5
.,.= °°095 105CC
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
2.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.05
BOTTOM VIEW—EXPOSED PAD
0.56 ± 0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
1.37 ±0.05
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DC6) DFN 1103
0.25 ± 0.05
1.42 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.61 ±0.05
(2 SIDES)
1.15 ±0.05
0.675 ±0.05
2.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
0.50 BSC
PIN 1
CHAMFER OF
EXPOSED PAD

LTC4069EDC-4.4#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Standalone Li-Ion Battery Charger w/ Thermistor Input, New 4.4V Batteries
Lifecycle:
New from this manufacturer.
Delivery:
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