RT7264A
14
DS7264A-01 September 2012www.richtek.com
©
Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
for switching regulator applications. However, care must
be taken when these capacitors are used at input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, V
IN
. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V
IN
large enough to damage the
part.
Thermal Shutdown
Thermal shutdown is implemented to prevent the chip from
operating at excessively high temperatures. When the
junction temperature is higher than 150°C, the chip is
shut down the switching operation. The chip is
automatically re-enabled when the junction temperature
cools down by approximately 30°C.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ
JA
, is layout dependent. For
WDFN-14L 4x3 package, the thermal resistance, θ
JA
, is
60°C/W on a standard JEDEC 51-7 four-layer thermal test
board. For SOP-8 (Exposed Pad) package, the thermal
resistance, θ
JA
, is 75°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at T
A
= 25°C can be calculated by the following
formulas :
P
D(MAX)
= (125°C − 25°C) / (60°C/W) = 1.667W for
WDFN-14L 4x3 package
Figure 7. Derating Curve of Maximum Power Dissipation
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0255075100125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
WDFN-14L 4x3
SOP-8 (Exposed Pad)
Four-Layer PCB
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the IC.
` Keep the traces of the main current paths as short and
wide as possible.
` Put the input capacitor as close as possible to the device
pins (VIN and GND).
` SW node is with high frequency voltage swing and
should be kept at small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pickup.
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the IC.
` Connect all analog grounds to a common node and then
connect the common node to the power ground behind
the output capacitors.
` An example of PCB layout guide is shown in Figure 8
for reference.
P
D(MAX)
= (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. The derating curve in Figure 7 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
